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WO/2014/133783A1 |
A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter....
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WO/2014/128687A1 |
A method of testing a frequency synthesizer over a predetermined frequency range using a delay unit complying with a spectral delay distribution model modeling a spectral delay distribution of the delay unit over the predetermined freque...
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WO/2014/130525A1 |
A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilize...
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WO/2014/130913A1 |
A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs an...
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WO/2014/120553A1 |
Fast phase coordinating systems and methods are disclosed. An example system includes a phase locator configured to detect a first phase of a reference signal and a first phase of a coordinating signal after the first phase of the refere...
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WO/2014/120911A1 |
The invention generally relates to phase locked loops (PLL), and more specifically to ultralow bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method ...
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WO/2014/119558A1 |
A DLL circuit comprises: a variable frequency division circuit that uses a variable frequency division ratio to frequency-divide a first clock signal, thereby generating first and second frequency-divided clock signals; a grain size chan...
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WO/2014/115657A1 |
This output-signal generation device contains the following: a phase adjustment unit that generates an output signal on the basis of an input signal and can perform an adjustment operation that sets the phase difference between the input...
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WO/2014/112509A1 |
This output signal generation device includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input ...
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WO/2014/108443A1 |
The present invention relates to a digital cavity for filtering an analog input signal. The digital cavity comprises: an analog-to-digital converter (11); a clock (15) arranged to provide a reference timing for the analog-to-digital conv...
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WO/2014/108845A1 |
Some demonstrative embodiments include devices, systems and/or methods of generating a frequency reference using a solid-state atomic resonator formed by a solid-state material including an optical cavity having color centers. A device m...
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WO/2014/109953A1 |
This disclosure includes systems and methods for frequency synthesis using a voltage-controlled oscillator (VCO) with a programmable array of capacitors. A suitable setting for the capacitor array may be derived through a non-successive ...
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WO/2014/107163A1 |
A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4GHz and 2.4GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integ...
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WO/2014/106899A1 |
In the present invention, control means (4) controls demultiplied frequencies from a frequency demultiplier (2) so that the output frequency from the frequency demultiplier (2) becomes a specified fraction of an integer of the oscillatio...
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WO/2014/105346A1 |
A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is div...
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WO/2014/105707A1 |
Aspects of the disclosure relate generally to a circuit (100) for sustaining an radio frequency (RF) modulated optical signal. The circuit may comprise a self injection locking component (107) having a fiber optic delay line (130) over w...
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WO/2014/098557A1 |
The present invention relates to a system (100) for determining frequency of a signal, comprising: an input (10) for receiving a signal; a delaying means (20) comprising a plurality of first delay cells (21), connected to the input (10) ...
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WO/2014/093890A1 |
Embodiments are disclosed of a multi-chip apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal depe...
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WO/2014/090136A1 |
A charge pump circuit used for a charge pump phase-locked loop includes a charging and discharging unit (601), a first complementary circuit unit (602), a first operational amplifier unit (A1), an inverter unit (603), a second complement...
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WO/2014/086134A1 |
A charge pump (1) capable of being quickly started. After an enable signal of the charge pump (1) arrives, in a very short period, a pump electricity capacitor and a load capacitor of the charge pump (1) are charged, and the process is c...
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WO/2014/082155A1 |
An offset phase locked loop synthesizer comprising: an input; an output; a voltage controlled oscillator (VCO), the VCO output coupled to the synthesizer output; a phase frequency detector having a reference input, a feed- back input, an...
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WO/2014/078279A1 |
A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to...
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WO/2014/073503A1 |
[Problem] To provide a reference signal generation device that is able to continue outputting an appropriate reference signal by making a correction with consideration of humidity even when an appropriate reference signal cannot be obtai...
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WO/2014/055204A1 |
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder (290), at least one digital frequency mismatch number; decoding, with the at least one decoder (290), the at ...
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WO/2014/045929A1 |
[Problem] To realize, at an extremely low cost, a standard signal generation device capable of performing self-running control even when an appropriate reference signal cannot be received. [Solution] The standard signal generation device...
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WO/2014/045551A1 |
A reception circuit, wherein in the first operation mode, the operation of at least a first charge pump circuit (32) from amongst: a phase/frequency comparator (31); the first charge pump circuit (32); samplers, other than the specified ...
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WO/2014/042546A1 |
The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of t...
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WO/2014/043531A1 |
A voltage controlled oscillator (VCO) core for cancelling a supply noise is described. The VCO core includes an input node that receives the supply noise. The VCO core also includes a noise path coupled to the input node. The VCO core ad...
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WO/2014/042820A1 |
Techniques are presented to reduce reversion leakage in charge pump circuits. The exemplary circuit is a charge pump of the voltage doubler type, where the output of each leg is supplied through a corresponding output transistor. An auxi...
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WO/2014/035743A1 |
A synthesizer architecture, responsive to a low noise reference signal from a discrete oscillator, provides a continuous periodic output with a period that is a fractional multiple of the low noise reference signal. One exemplary embodim...
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WO/2014/034955A1 |
An atomic oscillator includes an alkali-metal cell in which alkali-metal atoms are enclosed, a light source which irradiates the atoms in the alkali-metal cell with laser beams, a photodetector which detects a light amount of the laser b...
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WO/2014/031076A1 |
Various embodiments provide a control system for a hydrogen generator of a vehicle. The control system comprises: a controller and a voltage supplier. The controller is configured to receive a hydrogen indication which is a measure of hy...
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WO/2014/027036A1 |
According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the ...
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WO/2014/026029A1 |
Tunable injection locked (IL) dividers having enhanced locking range, good phase noise performance, and low power consumption are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes an oscillator and at lea...
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WO/2014/018444A2 |
A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputti...
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WO/2014/018893A1 |
A method includes generating a first signal based on a difference between a first frequency of a first voltage controlled oscillator (VCO) and a second frequency of a second VCO. The method further includes determining a gain of the firs...
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WO/2014/012180A1 |
An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the referen...
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WO/2014/013289A1 |
An electronic device has a calibration arrangement (120) for controlling a frequency characteristic of a PLL circuit having a phase comparator (112) having an output for generating a phase difference signal, a voltage controlled oscillat...
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WO/2014/008231A2 |
Oscillators are described that have a highly stable output frequency versus the variation of supply voltage and different operating conditions such as temperature. The concepts are broadly applicable to various types of oscillators. The ...
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WO/2014/008013A1 |
A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a ca...
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WO/2014/008002A1 |
A delay-locked loop (DLL) circuit is disclosed that can generate an output oscillation signal having a frequency that is an integer multiple of an input oscillation signal. The DLL includes a phase detector, a charge pump, and a voltage-...
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WO/2014/008071A1 |
A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. T...
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WO/2014/006439A1 |
An electronic device has a capacitive arrangement (100) for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respect...
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WO/2014/006654A1 |
A semiconductor device according to an embodiment comprises: a phase comparator which generates phase difference determination signals (UP, DN); control current generation circuits (211-21m) each of which is provided with a current sourc...
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WO/2014/008000A1 |
A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N-1 and N is a power of 2. The frequency divider also incl...
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WO/2013/190236A2 |
The invention relates to a device for supplying an electronic circuit (8) which includes applying a clock signal (H) having a clock frequency (Fappl), which includes: a frequency actuator (6) designed to generate the clock signal (H) in ...
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WO/2013/192456A1 |
A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal...
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WO/2013/185308A1 |
A frequency locking method comprises: a control unit generating auxiliary control voltage corresponding to target oscillation frequency and inputting the auxiliary control voltage to a voltage-controlled oscillator; and a loop filter inp...
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WO/2013/180766A1 |
A system can include a phase detector (105) configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter (110) coupled to the phase detector and configured to gen...
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WO/2013/177002A1 |
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between t...
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