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WO/2015/039330A1 |
In a method for mitigating the vibration-induced phase noise of an phase locked loop with an acceleration sensitive voltage controlled oscillator, a correction signal generated by applying a gain and a equalization to an acceleration sig...
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WO/2015/041645A1 |
Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection...
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WO/2015/038166A1 |
Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digita...
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WO/2015/038867A1 |
A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase- adjusted version of the clocking signal. The output of the edge sampler is used as a phase- error indicator for a filtered feedback loop that aligns...
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WO/2015/033156A1 |
A frequency discriminator comprising a power splitter (2) for splitting a signal (3) into first and second paths (4, 5), wherein the first path (4) is configured to provide a first, straight-through signal and the second path includes a ...
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WO/2015/030386A1 |
The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit section and an injection-locked phase-locked loop circuit section, thereby performing a f...
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WO/2015/025966A1 |
[Problem] To provide a phase-digital converter with which reduced power consumption is possible. [Solution] This phase-digital converter (1) has: first to 2n-th (n is an integer equal to 1 or greater) sample/hold units which, in sync wit...
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WO/2015/026472A1 |
A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from deita-sigma modulators. A first feedback ...
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WO/2015/021769A1 |
Disclosed is a frequency sweep signal generation circuit. The circuit comprises: a reference frequency source which generates a reference frequency signal; a first frequency synthesis circuit which operates over a first frequency band, h...
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WO/2015/017233A1 |
Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a f...
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WO/2015/014068A1 |
The present invention provides a radio frequency power supply system. The radio frequency power supply system comprises a radio frequency power supply, and an automatic impedance matcher electrically between the radio frequency power sup...
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WO/2015/010432A1 |
The present invention provides a frequency signal generation system and a display apparatus. The system comprises: a digital phase-locked loop which receives a source frequency signal; a loop filter, an input end of which is connected to...
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WO/2015/008108A1 |
A charge pump circuit (202) comprises a first bipolar transistor device (288) and a second bipolar switching device (286) arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching d...
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WO/2015/006192A1 |
One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The ...
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WO/2015/003004A1 |
FIR filters for compensating for fixed pattern jitter, and methods of constructing the same are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component 1 with the coefficients of the FIR filter se...
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WO/2014/205529A1 |
Frequency response generator circuit for identification devices that generates a signal that oscillates at a response frequency and can be used in RFID tags. The circuit calculates how many periods of a reference clock signal have to be ...
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WO/2014/209151A1 |
Navigation satellite receivers have a large number of channels, where phase discriminators and loop filter of a PLL operate in phase, with data bits and control of numerically controlled oscillator (NCO) carried out simultaneously on ...
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WO/2014/202230A1 |
The present invention relates to an apparatus and a method for generating RF signals, the pulse width and pulse position of which are modulated. The apparatus comprises a digital device (2, 3) which is intended to generate different phas...
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WO/2014/196890A1 |
A phase detector (32) for generating a phase difference signal (UP, DOWN) indicative of a phase difference between a first bi-level signal of frequency F1 (Fref) and a second bi-level signal of frequency F2 (Ffb) is proposed. The phas...
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WO/2014/109974A9 |
An apparatus for synthesizing wideband radio frequency signals in the microwave region has mostly digital components. The apparatus processes and converts a signal from a stable single-frequency electrical oscillator into a lower or high...
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WO/2014/191339A1 |
The invention relates to a frequency synthesis device (100) comprising: first means (102-112) for generating a periodic signal at a frequency f1; second and third means (114, 116) coupled to the first means and generating, from the f1 fr...
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WO/2014/194308A1 |
An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (f REF) at a controller and a time-to-digital converter (TDC), the controller and TDC b...
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WO/2014/191259A1 |
The invention relates to a device (100) for generating at least one frequency-stable periodic signal including at least: - a generator (102) able to generate at least a first periodic signal whereof the frequency spectrum includes at lea...
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WO/2014/188307A1 |
A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequ...
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WO/2014/187373A1 |
An apparatus comprises a ring oscillator comprising a plurality of delay cells connected in cascade，a main injection apparatus comprising a plurality of main buffers，wherein the main buffers receive a reference clock from their input...
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WO/2014/189772A1 |
A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal...
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WO/2014/183523A1 |
A delay phase-locking method and circuit. The method comprises: sending a reference clock signal to a master delay line for delay; performing phase detection on the delayed reference clock signal; and according to a phase detection resul...
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WO/2014/176674A1 |
Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a ra...
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WO/2014/178314A1 |
A transmission apparatus (1) transmits data signals to a reception apparatus (2) using a first clock generated on the basis of given clock signals, and switches an operating band of a PLL unit (112) to an operating band that includes a f...
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WO/2014/176673A1 |
A phase-locked loop is simultaneoulsy synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the h...
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WO/2014/175859A1 |
In some examples, a circuit is described. The circuit may include a voltage- controlled oscillator that may be configured to generate an output signal. The circuit may also include a control signal generation unit that may be configured ...
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WO/2014/175947A1 |
Methods, systems, computer-readable media, and apparatuses for locally generating and synchronizing oscillation signals in a phased array system are presented. Multiple sub-array modules are used for collectively transmitting any number ...
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WO/2014/171086A1 |
With a VCO (301) and an injection-locked frequency divider (303a) in a stopped state, an ILFD control unit (520) sets a control parameter for another injection-locked frequency divider (303b) on the basis of the frequencies of a referenc...
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WO/2014/168516A1 |
The invention relates to the field of instrumentation, radiolocation and telecommunication. The output of a reference frequency generator (1) is connected to the input of a high-order frequency multiplier (2), the output of which is conn...
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WO/2014/165214A2 |
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar re...
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WO/2014/164345A1 |
An integrated circuit device may have an internal oscillator for generating a system clock, a trimming logic with a trimming register for adjusting an oscillation frequency of the internal oscillator; a serial data receiver, wherein a se...
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WO/2014/161360A1 |
Disclosed is a method for compensating for a synchronization clock signal, comprising: when it is determined that a communications network element does not obtain a reference clock signal and therefore meets a clock signal compensation c...
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WO/2014/155079A1 |
According to the invention a controllable passive circuit element including: a first terminal and a second terminal; a passive circuit control input to which a control signal is applied; a first passive circuit component having a first i...
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WO/2014/155080A1 |
According to the invention a monolithically integrated non-oscillatory master frequency regulator for use with at least one slave oscillator, the master frequency regulator including: an arrangement of passive circuit elements having an ...
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WO/2014/158728A1 |
A gyroscope system comprises a MEMS gyroscope coupled to a drive system and a sense system. The drive system maintains the MEMS gyroscope in a state of oscillation and the sense system for receiving, amplifying, and demodulating an outpu...
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WO/2014/150575A1 |
In one design, an apparatus includes an oscillator, a divider, and a phase locked loop (PLL). The oscillator receives a control signal and provides an oscillator signal having a frequency determined by the control signal. The divider rec...
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WO/2014/150902A1 |
A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (RF) output signal. A mute amplifier is coupled t...
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WO/2014/149438A1 |
A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal and generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled t...
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WO/2014/150625A1 |
Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor...
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WO/2014/153472A1 |
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire opendrain link by determining a transition in a signal received from the multi-wire...
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WO/2014/150030A1 |
Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit co...
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WO/2014/139430A1 |
A circuit comprising a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals, and a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a fe...
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WO/2014/134777A1 |
A cycle slip detection method and a correction method of digital signals and a related apparatus, wherein the cycle slip detection method of the digital signals comprises: performing de-phase processing on a first digital signal so as to...
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WO/2014/136399A1 |
An injection-locked oscillator (100) is provided with: a ring oscillator in which a first amplification circuit (141) that comprises an N-channel MOS transistor (111) and P-channel MOS transistors (112, 113) and a second amplification ci...
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WO/2014/132556A1 |
One of a plurality of reception circuits for receiving transmitted signals comprises an oscillation circuit that generates, on the basis of an oscillation signal acquired from a crystal oscillator connected thereto, a differential signal...
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