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WO/2022/005905A1 |
An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sa...
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WO/2022/001940A1 |
Disclosed in the present application are a phase jitter compensation method, a phase jitter compensation module and a digital phase-locked loop. The phase jitter compensation method comprises: acquiring a phase error signal of the digita...
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WO/2021/259324A1 |
A clock sending apparatus and method, and a clock receiving apparatus and method. The clock sending apparatus comprises: an input unit (102), configured to input a first input clock and a second input clock; a sampling unit (104), config...
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WO/2021/259235A1 |
The present disclosure relates to a method for boosting the frequency of a clock signal, a clock circuit, and a digital processing device. More specifically, provided is a method for boosting the frequency of a clock signal, comprising: ...
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WO/2021/258751A1 |
A phase self-correction circuit, comprising a trigger signal operation module and a signal phase correction module, wherein the trigger signal operation module and the signal phase correction module each are composed of a plurality of di...
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WO/2021/261183A1 |
[Problem] To provide: a method for producing a highly reliable gas cell at low cost; and a method for producing an atomic oscillator using the same. [Solution] A main body substrate 10 is formed such that: a first opening 11 and a second...
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WO/2021/255739A1 |
A high-resolution adaptive digital frequency synthesizer Integrated Circuit (IC) for wireless power systems, which comprises a digitally controlled tunable ring-oscillator, based on a chain of delay-line cells (DLs) being adapted to gene...
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WO/2021/254606A1 |
A frequency determination device is disclosed for determining a frequency relationship between a reference signal and a clock signal. The frequency determination device comprises a plurality of constituent time-to-digital converters (TDC...
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WO/2021/244113A1 |
The present disclosure relates to a clock circuit, a computation chip, a hash board, and a data processing device. The clock circuit comprises M levels of clock driving circuits connected in series, wherein M is an integer not less than ...
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WO/2021/246150A1 |
Provided is a glass for atomic cells, whereby the oscillating frequency in an atomic oscillator is less likely to be changed over time.　The glass for atomic cells has a molar volume of 26.0 cm3/mole or less.
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WO/2021/243019A1 |
An analog to digital conversion (ADC) circuit includes a voltage-controlled oscillator (VCO)-based quantizer that receives a voltage input signal to be quantized and provides a digital output. A predictor samples the digital output, eval...
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WO/2021/237509A1 |
A clock and data recovery circuit, a processing chip and an electronic device. The clock and data recovery circuit comprises an edge detector, a flip circuit (2), a delay chain (3), a delay control module (4) and a clock delay module (5)...
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WO/2021/239978A1 |
A radio device (110) comprises a radio transceiver (105, 107), a resonator (101), a temperature measurement unit (102), a frequency synthesiser (113) and a processing system (104). A temperature signal from the temperature measurement un...
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WO/2021/236402A1 |
Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, gen...
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WO/2021/233203A1 |
A phase detection method, an apparatus thereof, and a device. The phase detection apparatus comprises a signal processing assembly, a phase discrimination component, and a phase comparison assembly. The signal processing assembly is conf...
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WO/2021/223737A1 |
A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider ci...
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WO/2021/219205A1 |
A calibration unit and method therein for calibrating a TDC comprised in a digital PLL are disclosed. The TDC receives a signal from a free-running DCO and a reference signal, and measures the time difference between the DCO and referenc...
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WO/2021/212554A1 |
A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to...
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WO/2021/213668A1 |
A Time to Digital Converter (TDC) arrangement (200) comprises a first delay circuit (230) configured to receive a signal with N phases; a set of phase detectors (240) configured to compare each phase of the signal with a reference signal...
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WO/2021/144393A9 |
The present disclosure relates to a phase-locked loop (PLL) based on a charge- sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capaci...
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WO/2021/197580A1 |
A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A f...
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WO/2021/202451A1 |
Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector, PFD, (3110) which outputs differential error clocks based on comparison of differential reference clocks and differen...
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WO/2021/196993A1 |
A clock signal generation circuit, a clock signal generation method and an electronic device, which relate to the technical field of communications. In the clock signal generation circuit, an initial clock provision circuit (10) may gene...
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WO/2021/194605A1 |
A phased locked loop (PLL) having a filter output voltage that is limited to a fraction of the voltage range accepted by the tuning port of a voltage-controlled oscillator (VCO) under control and a control system responsive to the filter...
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WO/2021/189835A1 |
A modular architecture integrated with wireless power supply and signal interaction, and an application. The modular architecture comprises a first module and a second module, wherein the modules comprise an integrated circuit, which use...
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WO/2021/191970A1 |
A transceiver (101) that receives signals in a super heterodyne format and comprises: a reference oscillator (29) that outputs a reference signal for a specific frequency; a PLL (28) that modulates the reference signal into a local signa...
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WO/2021/188252A1 |
Portable communications device (110) and method (500) for full duplex operation in a time division multiple access radio system. The method (500) includes providing a switch (340) for connecting one of a first voltage controlled oscillat...
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WO/2021/184632A1 |
The present invention provides a lock detection method for a phase-locked loop, the phase-locked loop, and a frequency-locked detection controller thereof, is capable of solving the problem of an internal logic exception during an unstab...
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WO/2021/180927A1 |
Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference...
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WO/2021/178147A1 |
An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality...
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WO/2021/174420A1 |
A phase-locked loop circuit, comprising: a frequency/phase detector (11), a first voltage control module (12), a second voltage control module (13), a third voltage control module (14), a voltage-controlled oscillator (15), and a frequen...
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WO/2021/178038A1 |
The present disclosure provides methods and systems for performing non-classical computations. The methods and systems generally use a plurality of spatially distinct optical trapping sites to trap a plurality of atoms, one or more elect...
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WO/2021/175114A1 |
Some aspects of the present disclosure relate to detection of a Phase Hit and, upon detecting the Phase Hit, determining the magnitude and location of the Phase Hit. Detecting the Phase Hit may involve comparing a phase offset difference...
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WO/2021/177072A1 |
A radar device (1) is provided with: a transmission unit (10) for transmitting an FMCW signal; a reception unit (20) for receiving the FMCW signal transmitted by the transmission unit (10) and reflected by an object (60); a measurement u...
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WO/2021/169158A1 |
A frequency divider and an electronic device. The frequency divider comprises: a frequency dividing ratio selection module (1), configured to output a first level setting value as a frequency dividing ratio setting value in response to a...
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WO/2021/168552A1 |
A "frequency shifter" is a clock synthesis system, that includes either a multiplexer or a multi- modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchroni...
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WO/2021/166176A1 |
This phase synchronization circuit has: an oscillation circuit (203) that includes a variable current generation unit (222) for generating a variable current of a current amount corresponding to a control voltage and a fixed current gene...
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WO/2021/164881A1 |
A hybrid Phase Locked Loop, PLL (10, 34A, 34B, 38) employs an analog control loop during a first period of operation, such as steady-state operation, to achieve a simple design, stable operation at very high frequency, and low phase nois...
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WO/2021/165459A1 |
The present invention relates to a reference oscillator arrangement having a first reference oscillator for generating a first output signal and a second reference oscillator for generating a second output signal, the reference oscillato...
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WO/2021/166131A1 |
In a wireless power transmitting device (10): a control circuit (11, 21, 31) outputs a control signal for setting a frequency and phase of an F-PLL signal generated by an F-PLL (12, 22, 32); the F-PLL (12, 22, 32) generates the F-PLL sig...
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WO/2021/156545A1 |
A control arrangement is disclosed for providing a plurality of phase-coherent oscillating signals. It comprises a reference clock signal arrangement for providing a high-frequency reference clock signal and a plurality of modules (130) ...
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WO/2021/146946A1 |
Disclosed is an oscillator. The oscillator comprises two inverting amplifier elements, wherein each of the inverting amplifier elements forms a self-feedback structure by means of an inductor. Output ends of the two inverting amplifier e...
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WO/2021/150150A1 |
A Phase Locked Loop PLL circuit (100) and method therein for generating multiphase output signals are disclosed. The PLL circuit (100) comprises a digitally controlled oscillator (110), a sample circuit (120), an analog to digital conver...
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WO/2021/150457A1 |
A clock data recovery circuit (130) includes a phase detector (PD) (202) having a data input, a second input, and an output. The circuit (130) also includes a filter (208), first and second charge pumps (204, 206), a voltage-controlled o...
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WO/2021/146476A2 |
A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the ...
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WO/2021/142828A1 |
Provided is a time synchronization method, comprising: an adjustment stage, wherein the adjustment stage comprises N adjustment periods, and N is an integer greater than one. The adjustment stage comprises: in each adjustment period, gen...
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WO/2021/139746A1 |
A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequ...
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WO/2021/138730A1 |
A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillato...
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WO/2021/135303A1 |
Provided is an FPGA-based design method for equally dividing an interval, comprising the following steps: dividing the number of vibration periods of a second pulse signal of a crystal oscillator clock of an FPGA board card by the number...
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WO/2021/138294A1 |
An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divid...
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