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WO/2024/082527A1 |
Provided in the embodiments of the present disclosure are a delay phase-locked loop and a memory. When starting to operate, the delay phase-locked loop determines a phase difference between a reference clock signal and a feedback clock s...
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WO/2024/036322A3 |
An apparatus comprising: a digital integrator to generate a frequency error signal at least partially based on a digital phase error signal; and a logic circuit to set an integrated value of the digital phase error signal stored at a reg...
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WO/2024/078230A1 |
The present application provides a crystal oscillator, a control method for a crystal oscillator, a device, and a storage medium. The crystal oscillator comprises: an external crystal, a capacitance tuning array connected to the external...
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WO/2024/081461A1 |
A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive ...
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WO/2024/080571A1 |
A clock phase calibration device according to one embodiment of the present disclosure comprises: a clock generation module for generating a plurality of clocks on the basis of a reference clock; a clock sampling module for sampling sign...
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WO/2024/077088A1 |
A pathogen detection method. A sample that potentially contains a pathogen is collected. A triangle wave form output is produced. A signal associated with the triangle wave form is transmitted from a voltage-controlled oscillator over a ...
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WO/2024/067768A1 |
The present disclosure provides a burst mode clock and data recovery module, comprising: a data sampling sub-module configured to sample received data according to a clock signal, and output a sampling result to a phase determination sub...
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WO/2024/072977A1 |
A subordinate clock includes a first servo loop, a second servo loop, and a third servo loop, each include a respective digitally controlled oscillator (DCO). The first DCO receives (i) a first error signal that is associated with a phys...
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WO/2024/064574A1 |
Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) o...
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WO/2024/064546A1 |
Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An exam...
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WO/2024/064528A1 |
Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a fi...
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WO/2024/059587A1 |
An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by ...
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WO/2024/059586A1 |
An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the f...
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WO/2024/057606A1 |
A mechanical resonator-based oscillator comprises an input signal generator configured to output an input signal, a mechanical resonator comprising a body configured to vibrate according to the input signal and to output a vibration sign...
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WO/2024/055589A1 |
The present invention relates to a phase tracking circuit and method, and an electronic device. The phase tracking circuit may comprise: a frequency divider, which is used for performing frequency division processing on a first clock sig...
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WO/2024/051281A1 |
A frequency multiplier, a signal transmitter, and a radar chip. The frequency multiplier comprises: a signal generator, used for receiving a frequency modulated continuous wave (FMCM) signal, and outputting a square wave signal having th...
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WO/2024/051178A1 |
Provided is an oscillator circuit (100), comprising a frequency setting circuit (110), first and second clock signal generation circuits (120, 130), a clock synchronization circuit (150), a control circuit (140), and an output circuit (1...
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WO/2024/053527A1 |
A metal gas sealed cell 100 comprises: a cell body 10; a glass plate 11; an optical chamber 14 that is provided to at least one selected from the cell body 10 and the glass plate 11, and that is in communication with a gas generation uni...
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WO/2024/052063A1 |
A signal generating circuit (1100) comprising a series of cascade elements (1103a, 1103b), each comprising a cascade input, a cascade output; a clock input, a reset element (1115, 1117), and a first switch (1105a, 1107a) and a second swi...
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WO/2024/049732A1 |
A pulse generator circuit (210) includes a charge pump (114) having a charge pump output. A voltage divider (R1/R2) is coupled to the charge pump output. The voltage divider (R1/R2) has a voltage divider output. An error amplifier (116) ...
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WO/2024/044910A1 |
A photosensitive ring oscillator, its preparation method, and a flexible artificial retina. The photosensitive ring oscillators (PROs) based on 2D semiconducting materials have been fabricated on flexible biological compatible substrates...
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WO/2024/045130A1 |
Provided in the present invention are a measurement circuit and an operation method therefor. The measurement circuit comprises: a voltage source (V1); a ground (G1); a first resistor (R1), wherein a first end of the first resistor (R1) ...
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WO/2024/049968A1 |
A timing alignment circuit (108) includes detection circuitry (138, 142) to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a ...
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WO/2024/049818A1 |
A digital-to-time converter circuit (200) includes a scrambling and noise shaping circuit (211), a digital-to-analog converter (DAC) (208), and a buffer circuit (218). The scrambling and noise shaping circuit (211) includes an input and ...
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WO/2024/043985A1 |
A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a vol...
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WO/2024/031746A1 |
Provided in embodiments of the present disclosure are a delay phase-locked loop, a clock synchronization circuit and a memory. The delay phase-locked loop comprises a preprocessing module, which is configured to receive an initial clock ...
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WO/2024/031169A1 |
A module for modulation and demodulation using two substantially identical self-oscillating mixers (SOMs) injection-locked at a coupling frequency, providing a simple compact, low power, highly efficient receiver, transmitter or transcei...
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WO/2024/036322A2 |
A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.
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WO/2024/026054A1 |
In some examples, a circuit (104) includes a phase frequency detector (PFD) (206) having a first input, a second input, and an output. The circuit also includes a control circuit (208) having an input and an output, the control circuit i...
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WO/2024/016896A1 |
Disclosed in the present application are a multi-phase clock generation circuit and method. The circuit comprises: a frequency division module, wherein a signal input end of the frequency division module receives and connects to a clock ...
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WO/2024/016951A1 |
The present invention relates to a duty cycle adjuster, comprising: a first duty cycle adjustment (DCA) module, wherein the first DCA module comprises M adjustment units, which are connected in parallel, each adjustment unit comprises an...
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WO/2024/019493A1 |
An electronic device according to an embodiment disclosed in the present document may comprise an antenna, a transceiver, an amplifier disposed on a transmission path electrically connected to the antenna and the transceiver, a filter el...
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WO/2024/015151A1 |
A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscilla...
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WO/2024/011768A1 |
The embodiments of the present disclosure relate to the field of semi-conductors, in particular to a delay detection circuit of a delay-locked loop, a delay-locked loop circuit, and a storage apparatus. The delay detection circuit of the...
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WO/2024/015674A1 |
An apparatus for synchronizing frequency to a symbol timing, the apparatus including: a master oscillator to generate a master clock signal; an interpolator to accumulate a frequency error estimate between a symbol timing frequency and t...
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WO/2024/008579A1 |
A delay-locked loop, DLL, circuit (10) for generating a signal that has a defined delay or phase shift comprises a pulse generator (12) configured to generate a pulse signal (Spulse) that is input to a circuit (14) having an unknown dela...
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WO/2024/008299A1 |
A transmitter is disclosed for operation with restricted power consumption. The transmitter comprises a signal generation oscillator configured to provide a signal for transmission, a phase-locked loop (PLL) configured to calibrate an os...
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WO/2024/005919A1 |
A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The com...
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WO/2024/006590A1 |
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock...
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WO/2024/006589A1 |
One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal g...
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WO/2024/006614A1 |
One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The ...
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WO/2024/005813A1 |
For example, a Local Oscillator (LO) generator may include a plurality of frequency sources configured to provide a respective plurality of frequency source signals according to a first frequency; and an injection-locked frequency divide...
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WO/2023/247081A1 |
A phase-locked loop circuit (10) comprises an analog part(15), an integral part (17), and a voltage controlled oscillator (19) configured to receive a first current signal from the analog part (15) and a second current signal from the in...
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WO/2023/249341A1 |
A wireless communication device and method for controlling activation of a radio frequency (RF) transmission signal generation circuit are disclosed. The wireless communication device may comprise a communication processor, and a transce...
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WO/2023/243091A1 |
This phase synchronization control circuit (12) comprises: a phase difference detector (20) that detects a phase difference (Δθ) between an AC voltage (VI) and an AC signal (vac); a frequency control unit (21) that generates a first fr...
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WO/2023/236398A1 |
A phase-locked loop, a signal processing device and a signal processing method. In the phase-locked loop, a reference clock unit outputs two or more frequency-adjustable synchronous reference clock signals to a phase discrimination unit;...
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WO/2023/233642A1 |
This phase comparator comprises: a phase frequency comparator (1) which compares the phases of a reference clock signal and a feedback clock signal, and outputs, on the basis of the phase difference, a voltage up signal and a voltage dow...
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WO/2023/235023A1 |
A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the d...
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WO/2023/232255A1 |
A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integr...
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WO/2023/234059A1 |
A phase synchronization circuit according to one embodiment of the present disclosure comprises: a signal generation unit that has a plurality of delay units connected in series, and can output a first signal resulting from delaying an i...
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