| Document |
Document Title |
|
WO/2020/012550A1 |
This phase synchronization circuit comprises: a first delay circuit (311) that delays a first reference clock signal by an adjustable first delay amount and outputs a first delayed reference clock signal; first clock control circuits (31...
|
|
WO/2020/013917A1 |
Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also...
|
|
WO/2020/012557A1 |
This phase-locked loop circuit is configured to comprise: a frequency division ratio control circuit (8) that, in synchronization with a frequency division signal output from a variable frequency divider (7), controls the frequency divis...
|
|
WO/2020/009833A1 |
A voltage controlled oscillator (VCO) is disclosed to provide reduced phase noise at higher operating frequencies. A buffer-first VCO configured according to an embodiment includes multiple VCO core circuits configured to provide synchro...
|
|
WO/2020/008573A1 |
A frequency modulation oscillation source (100) comprises: a voltage-controlled oscillator (5) in which oscillation frequency is controlled on the basis of a modulation control voltage generated by integrating a comparison result signal ...
|
|
WO/2020/006989A1 |
Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a prev...
|
|
WO/2020/005432A1 |
Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip ...
|
|
WO/2020/003514A1 |
This phase amplitude controlled oscillator is configured such that a first controller (5) and a second controller (6) control the phase of an output wave after synthesis by a synthesizer (4), by shifting the phases of the oscillation fre...
|
|
WO/2019/240961A1 |
According to one embodiment, a millimeter-wave (mm-wave) frontend integrated circuit includes an array of mm-wave transceivers, where each of the mm-wave transceivers transmits and receives coherent mm-wave signals with variable amplitud...
|
|
WO/2019/241424A1 |
Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decision...
|
|
WO/2019/232610A1 |
A compensation circuit for an oven-controlled crystal oscillator serving as a reference for a phase-locked loop in holdover mode is disclosed. A non-linear function module generates a modified aging signal that is a non-linear function o...
|
|
WO/2019/236936A1 |
In examples, a voltage-controlled oscillator (VCO) (110) comprises an inductor (118); a first pair of transistors (128, 130) having first terminals (103, 101) coupled to a voltage source (132), second terminals (109, 105) coupled to oppo...
|
|
WO/2019/231774A1 |
According to one embodiment, a dual voltage controlled oscillator (VCO) circuit includes a first VCO and a second VCO. The first VCO includes: a first variable capacitor having an input node, a first output node, and a second output node...
|
|
WO/2019/231523A1 |
Oscillator calibration circuits and wireless transmitters including oscillator calibration circuits. An oscillator calibration circuit includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC ...
|
|
WO/2019/231857A1 |
An example sigma delta modulator (SDM) circuit includes a floor circuit (306), a subtractor (308) having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage ...
|
|
WO/2019/231771A1 |
According to one embodiment, a phase locked loop (PLL) circuit includes a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency and a second VCO to generate a second signal having a second frequenc...
|
|
WO/2019/228054A1 |
Embodiments of the present application provide a phase locking device and a phase locking method. The phase locking device comprises an amplitude adjustment unit, an amplitude and phase discriminator connected to the amplitude adjustment...
|
|
WO/2019/225135A1 |
A PLL circuit according to the present disclosure comprises: a divider (5) that divides a reference clock signal and outputs a divided clock signal; a phase comparator (2, 22) that compares the phases of the reference clock signal and th...
|
|
WO/2019/067194A9 |
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data...
|
|
WO/2019/223876A1 |
A device for measuring the delay of a delay line in a phase-locked loop comprising an oscillator, the device being configured to: determine a difference between a first oscillator phase at a first time and a second oscillator phase at a ...
|
|
WO/2019/222245A1 |
A phase-locked loop circuit (100) includes a first time-to-digital converter (TDC) (102) to receive an input reference signal (101), a digital-controlled oscillator (DCO) (116), and a first divider (130) coupled to an output of the DCO (...
|
|
WO/2019/210473A1 |
Provided are a clock data recovery apparatus, an optical line terminal and a passive optical communication system. The clock data recovery apparatus comprises: a phase detection loop unit, a frequency oscillation unit, a frequency detect...
|
|
WO/2019/212662A1 |
Exemplary systems, apparatus, and methods described herein may improve a scan process for near field communications, such as IEEE 802.15.4. The improvements may include, during the scan process, performing one of increasing a current of ...
|
|
WO/2019/213654A1 |
A time-to-digital converter circuit (100) includes a logic gate (130) configured to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate (130) i...
|
|
WO/2019/209495A1 |
A resonance system is disclosed, which includes a first resonance device configured to receive a drive signal and generate an output signal, a second resonance device configured to receive a control signal and generate the drive signal b...
|
|
WO/2019/205177A1 |
A phase locked loop, comprising: an oscillator; a digital switch capacitor array connected in parallel to a varactor in the oscillator, the digital switch capacitor array comprising N switch capacitors connected in parallel, and N being ...
|
|
WO/2019/201260A1 |
A local oscillator (LO) distribution system is described. The LO system includes a plurality of phase-locked loop (PLL) modules coupled to each other in a one-way, circulant coupling topology. Each PLL module receives a reference clock s...
|
|
WO/2019/191895A1 |
Provided are a phase-locked loop and a terminal device. The phase-locked loop comprises: a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator. The phase detector is connected to the low-pass filter by m...
|
|
WO/2019/190567A1 |
A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than...
|
|
WO/2019/183866A1 |
A frequency generator, comprising a control unit for receiving an input signal to generate a divisor signal, a phase signal and a cycle signal; a frequency divider for receiving the input signal, and performing integer frequency division...
|
|
WO/2019/190558A1 |
Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock l...
|
|
WO/2019/191455A1 |
Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase e...
|
|
WO/2019/185054A1 |
A frequency multiplier, a digital phase lock loop circuit and a frequency multiplying method. The frequency multiplier comprises: a clock controller for receiving an output signal from a time-to-digital converter in a digital phase lock ...
|
|
WO/2019/183943A1 |
Provided in an embodiment of the present invention are an automatic amplitude control device and method. The device comprises: an oscillator and a current source array, wherein one terminal of the current source array is coupled with a s...
|
|
WO/2019/188990A1 |
[Problem] To provide a technique, with respect to an oscillating device that uses a crystal oscillator and stabilizes an oscillating frequency on the basis of an external clock signal, for stabilizing the oscillating frequency that is ou...
|
|
WO/2019/182642A1 |
A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an ana...
|
|
WO/2019/182697A1 |
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more...
|
|
WO/2019/178748A1 |
A frequency generator. The frequency generator comprises a sigma-delta modulator for generating a divisor control signal and a phase control signal; an oscillator for generating an oscillation signal, the oscillation signal having a firs...
|
|
WO/2019/178174A1 |
A phase-locked loop (PLL) includes a selection circuit (102) including multiple inputs, each input to receive a separate reference clock. A programmable reference clock divider (104) divides down the reference clock selected by the selec...
|
|
WO/2019/178176A1 |
A phase-locked loop (PLL) system (100) includes a first PLL (170) coupled to receive a first reference clock. The PLL system (100) also includes a second PLL (140) coupled to receive a second reference clock. The output of the second PLL...
|
|
WO/2019/177532A1 |
A divider synchronization device (100) is disclosed, which comprises at least first and second circuit portions (102, 104) configured to generate respective radio signals for multichannel transmission, each circuit portion having a proce...
|
|
WO/2019/177945A1 |
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler (202) configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data ...
|
|
WO/2019/171585A1 |
A first pulse selector (7a) outputs an output signal of a variable frequency divider (3) to phase frequency comparators (4a-4d) in a time divisional manner. A second pulse selector (7b) outputs a reference signal from a reference signal ...
|
|
WO/2019/171607A1 |
The purpose of the present invention is to provide an oscillation device which achieves both expansion of frequency variable width and refinement of the variable pitch thereof. An oscillation device 1 is provided with: an oscillation uni...
|
|
WO/2019/173821A1 |
A circuit includes a time-to-digital converter (TDC) (102) to produce an output signal that is a function of a time difference between a first input clock to the TDC (102) and a second input clock to the TDC (102). A first delay line (50...
|
|
WO/2019/172467A1 |
A phase-locked loop (PLL) apparatus and a method for clock synchronization are disclosed. According to an embodiment, the PLL apparatus comprises an adjustable oscillator, one or more first difference determiners, one or more first param...
|
|
WO/2019/169607A1 |
A charge pump circuit for suppressing current mismatch and a control method therefor, and a phase locked loop circuit, relating to the technical field of communications. The charge pump circuit comprises: a first control circuit (10), a ...
|
|
WO/2019/167670A1 |
The present art relates to a phase-locked loop circuit that enables power consumption to be reduced. The phase-locked loop circuit comprises: an SAR-ADC that includes two capacitors and outputs a comparison result of voltages occurring a...
|
|
WO/2019/168452A1 |
Embodiments of the present disclosure provide methods and apparatus for demodulating a received signal. For example, a demodulation system for demodulating an input signal is provided. The input signal comprises a carrier wave modulated ...
|
|
WO/2019/164625A1 |
An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit t...
|
