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Patent Searching and Data


Matches 451 - 500 out of 6,167

Document Document Title
WO/1995/020198
A method and system for formatting numerical information. An object-based operating system provides various number formatting services. Some objects scan text and convert the text to numerical information, and convert non-text numerical ...  
WO/1995/010897
The present invention relates to a method for carrying out buffering in a digital telecommunication system, wherein data is transferred in frames the length of which is F bits. According to the method, data is written into the buffer mem...  
WO/1995/009398
A system for transmitting instructions in a processor node (200), where the communications processor (3) has a cache memory (6) of known capacity, comprises means for copying instructions (9) directly on the fly via the memory bus (4) to...  
WO/1995/006285
A data aligner transfers data from an input having N+1 byte lanes to an output having N+1 byte lanes. The data aligner includes a write data aligner and a read data aligner. The write data aligner includes a write shifter coupled to the ...  
WO/1994/019743
An intermediate processor (22) includes a main processor coupled to a plurality of front end circuits, and each front end circuit is coupled to a plurality of control unit interface circuits. Each control unit interface circuit is couple...  
WO/1994/017476
Interface apparatus for connection between a data handling device and a data communication medium to enable data to be transferred between the device and the medium, comprises a data alignment device (7, 8) coupled in use to the data han...  
WO/1994/017470
A queue system comprising a plurality of queues (20-23) where each is defined by a set of criteria, the queue system comprises a plurality of header registers (1-3) where each header register defines a queue in the queue system and a plu...  
WO/1994/015269
A system and method for allowing a component having a first byte ordering to effectively transfer information to another component having a second byte ordering. The present invention envisions embodiments where facilitation of the infor...  
WO/1994/012983
The invention provides fast generation of flag signals for devices, such as first-in first-out buffers, by looking-ahead and predetermining flag signals for possible future states of the device. The look-ahead signal generator, in one em...  
WO/1994/011811
A method and system for creating multi-lingual computer programs by dynamically loading messages is provided. In a preferred embodiment, a user specifies a preferred language in which the computer program will communicate. The computer p...  
WO/1994/011800
A low cost, high speed data storage system provides word-by-word stale data detection while avoiding the need to both read and write a single memory location during a memory read operation. Two flag data storage bits are provided for eac...  
WO/1994/009434
A method and apparatus is disclosed for partitioning a data buffer to create separate read and write buffers, wherein the boundaries between the buffers and the sizes of the buffers change dynamically depending upon the command mix recei...  
WO/1994/007199
A data path aligner transfer data from an input having N byte lanes with byte enable bits to an outpout having N byte lanes. The aligner includes first stage (S1(0) - S1(2)) having N-1 selector/registers, and a second stage (S2(0) - S2(3...  
WO/1994/003983
A single clock cycle adaptive data compressor/decompressor (1/2) with a string reversal mechanism (6) is described which can perform data compression and decompression at the rate of one uncompressed symbol per clock cycle. The compresso...  
WO/1993/025031
The invention relates to a method and an equipment for monitoring the fill rate of an elastic buffer memory used in a synchronous digital telecommunication system, such as the SDH or SONET system. To enable the monitoring of the fill rat...  
WO/1993/021595
Method and apparatus for selecting samples for presentation on an output device, such as a display (24) or speaker (18), from a sequence of stored media samples, such as audio or video information. Position information is received from a...  
WO/1993/021575
A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the ...  
WO/1993/020516
A system and method for queuing, control and transfer of data between a host processor and a peripheral processor using an architecture and a data flow strategy of one or more virtual FIFO data structures stored in main memory and a hard...  
WO/1993/020506
A semiconductor floor plan layout for integrating a Data Dependency Checker (DDC) circuit and a Tag Assignment Logic (TAL) of a Register Renaming Circuit (RRC) circuit to conserve valuable semiconductor real estate. Floor plans of the pr...  
WO/1993/018922
An additional control device is mounted on an electronic equipment, and a large amount of data is transferred from the electronic equipment to the additional control device. An electronic control equipment in a printer outputs data to a ...  
WO/1993/018595
The SPE of an incoming STS-3 type signal is demultiplexed into three STS-1 payloads and fed to three FIFOs (45-1, 45-2, 45-3), and a byte which is synchronous with the TOH is tracked through the three FIFOs (45-1, 45-2, 45-3) to provide ...  
WO/1993/017381
A system performs dynamic segmentation analysis of attributes of a linear network, when the attributes are stored in a computer readable relational database. An embodiment of the system has an arrangement for converting data in the relat...  
WO/1993/014456
A barrel shifter capable of shifting input data in both directions, left and right, without increasing its circuit scale. In a barrel shifter unit circuit of a plural-stage barrel shifter, provided are a tristate buffer (11X) for left-sh...  
WO/1993/012600
A digital clock dejitter circuit includes a RAM (20) for receiving an incoming gapped signal (14a), a digital, fractional RAM fullness gauge (30) for tracking the average input and output rates to and from the RAM and for generating ther...  
WO/1993/012481
A data buffer that compensates the differences in data rates, between a storage device and an image compression processor. A method and apparatus for the real time indexing of frames in a video data sequence.  
WO/1992/022141
A series of data processors (20a-20n) operate on a body of data to convert it to compressed form for storage or transmission. The processors are connected in series such that the output of one processor is the input to the next processor...  
WO/1992/020028
Communication controller (3), for buffering data packets, interfaceable with a host processor (1) and a communication medium control unit (2) employing packet numbers assignment storing in a transmit queue (9) and a receive queue (10). E...  
WO/1992/020176
A method of and apparatus for allocating memory for storage of vocabularies used in adaptive data compression of a frame-multiplexed data stream of a data communications network. More specifically, a memory (Fig.1, VA; Fig.3, 40) of a da...  
WO/1992/017023
An information processing methodology gives rise to an application program interface which includes an automated digitizing unit, such as a scanner (210), which inputs information from a diversity of hard copy documents and stores inform...  
WO/1992/015159
An apparatus and method for clock rate matching in independent networks is disclosed. The apparatus accepts data from a modem (126) into a buffer (400) and determines the difference between the rate of the data entering the buffer (400) ...  
WO/1992/015055
Disclosed is a circuit designed to connect a microprocessor system (MP) to a communications channel (K) for series data transmission, the circuit ensuring optimum data transmission. This is done by the use of two first-in/first-out memor...  
WO/1992/010035
Improved means and methods are provided for transmitting binary data on a communication system, such as E-mail, which restricts the number of acceptable characters that can be transmitted. In a preferred embodiment, the binary data to be...  
WO/1992/009032
A bit disposal apparatus includes a register (16) which is divided at a truncation point (14) into a left register segment (18) and a right register segment (28), wherein bits to be disposed of are contained in the right register segment...  
WO/1992/008304
An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO (20) for receiving the data component (12) of the STS-1 signal, a measuring circui...  
WO/1992/008186
The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one...  
WO/1992/008192
A system is provided including a host processor and an audio capture and playback adapter having a DSP co-processor. The adapter includes shared memory accessible from both the DSP and the host. A DSP program is periodically written to t...  
WO/1992/002999
An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency. A circuit (43a) for extracting the SPE bytes from the first SONET sign...  
WO/1992/002018
A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers (62, 76) having grey code counters which reduce code conversion logic and which are less...  
WO/1991/018346
A device for transmitting a synchronous data which transmits data asynchronously from a first system controller to a second system controller. Transferred data is doubly stored in a first and a second memory. The data outputted from the ...  
WO/1991/013398
A digital storage device is provided that includes a storage unit (12) having a plurality of word storage locations (14), each of the word storage locations being coupled to a corresponding read enable line (R) and write enable line (W),...  
WO/1991/013396
A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architectur...  
WO/1991/013397
A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.  
WO/1991/010999
A method for compressing user data for storing on tape (10) comprising the steps of: receiving a stream of user data words organised into a plurality of records (CRn); compressing the user data according to a compression algorithm involv...  
WO/1991/011058
A method and apparatus is disclosed for providing modulation or compression encoding and decoding. A decoder effectuates a direct enumeration algorithm to accomplish a mapping and includes a ROM (1204) for receiving a signal representing...  
WO/1991/010955
The invention relates to an address processor for a signal processor. This address processor comprises means for address calculation in a read/write memory containing at least one circular buffer for storing state variables of digital fi...  
WO/1991/011000
A method for compressing user data for storing on tape (10) comprising the steps of: receiving a stream of user data words organised into a plurality of records (Rn); compressing the user data according to a compression algorithm involvi...  
WO/1991/007830
Clock dejitter circuits are provided and comprise control circuits (30) for generating a plurality of pulses over a clock cycle, and clock circuits (60) for tracking the speeds of jittered incoming data signal and based on those speeds, ...  
WO/1991/003880
The improved data compression system (100) concurrently processes both strings of repeated characters and textual substitution of input character strings. In this system (100), the performance of data compression techniques based on text...  
WO/1990/016025
Apparatus for connecting an additional data storage device to a computer port, such as a printer port, that is not necessarily adapted for connection to a data storage device. An interface circuit comprises means for reading stored multi...  
WO/1990/015385
A multiport register set (50) has an eight deep addressable stack (52) of N-bit wide data words (54). The stack (52) has a port (56) at the bottom of the stack and a port (58) at the top of the stack. A read counter (59) is connected by ...  

Matches 451 - 500 out of 6,167