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Patent Searching and Data


Matches 451 - 500 out of 9,225

Document Document Title
WO/2000/077786A1
When data are transferred from a host CPU (14) to a sound processor (24) which reproduces music sounds on a real-time basis, the burden on the host CPU (14) is greatly reduced. Upon transfer of music sound data from the host CPU (14) as ...  
WO/2000/073872A2
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by...  
WO/2000/068794A1
The aim of the invention is to facilitate a secure writing of a pointer (P) that points to the respective actual data set in a cyclic memory or a circular memory such as an EEPROM. To this end, the new data set (D'#3) is written into the...  
WO/2000/068774A1
A computer system (AP1) includes a RAM-based FIFO (20) for buffering communications between a host processor (10) and a remote serial-communications device (16). The FIFO provides for quadlet, doublet, and singlet transfer widths dependi...  
WO2000022890A3
The present invention provides for a unique microchip or circuit which can, inter alia, handle both current conducting functions and man-machine-interface functions in an electrical device, for example, such as a flashlight. The man-mach...  
WO/2000/062154A1
A cyclic buffer is implemented using logical blocks corresponding to the physical blocks of the buffer. The logical blocks are mapped to the physical blocks of the cyclic buffer, and are used to create an index to the buffer. Each entry ...  
WO/2000/062153A1
The present invention relates to a buffer device of the first-in-first-out type. The buffer device comprises a data inlet In, a data outlet Out and a storage buffer MEMFIFO1. The buffer device also comprises an integrated circuit IC, whi...  
WO/2000/060749A1
An interleave/deinterleave processing in which input data is arranged and stored in a storage area having continuous addresses of a RAM (103), the stored data is read with double precision in order of address of the RAM (103) according t...  
WO/2000/057268A1
A system (20) converts data from input field types to output field types. The system (20) receives a plurality of input attributes and output attributes from an application program (10), dynamically generates a plurality of data field co...  
WO/2000/054141A1
The invention relates to a system and a method for temporary decoupling of selection, processing and elimination of data to be transmitted or received from pure transmission or reception of data telegrams of a data bus. Temporary decoupl...  
WO/2000/054163A1
An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data ...  
WO/2000/052567A1
The invention relates to a system for transmitting data records that are divided into a plurality of words between two control units (5, 20). The inventive system comprises a memory configuration having a first memory (A) and a second me...  
WO/2000/049492A1
Systems and methods for transferring very large data files to a remote location (17). The systems and methods fragment the very large data file into smaller ordered blocks using file conversion software (11a) loaded onto a computer proce...  
WO/2000/049485A1
A circuit (34) receives data asynchronously from a bus (48) on which the data is transferred on both rising and falling edges of a control signal (H-STROBE), and provides the data to an output (FIFO_DIN) synchronously with a local clock ...  
WO/2000/046949A1
To synchronize a regulary occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an ou...  
WO/2000/046661A1
The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a numb...  
WO2000038112A3
A code compaction based on macro substitutions is presented wherein the choice of possible macro substitutions is guided by an evolutionary algorithm process. In a preferred embodiment, a random population of sets of macro substitutions ...  
WO/2000/038112A2
A code compaction based on macro substitutions is presented wherein the choice of possible macro substitutions is guided by an evolutionary algorithm process. In a preferred embodiment, a random population of sets of macro substitutions ...  
WO/2000/038063A2
A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first ident...  
WO/2000/038045A1
A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains th...  
WO/2000/033166A1
Methods and apparatus for implementing a technique for determining a data rate of a serial bitstream using pattern recognition and for matching a clock speed of a deserializer to that data rate. In one implementation, a port (100) for co...  
WO/2000/022513A1
A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A-B-L+S, wherein A is the total number of bytes alloc...  
WO/2000/022890A2
The present invention provides for a unique microchip or circuit which can, $i(inter alia), handle both current conducting functions and man-machine-interface functions in an electrical device, for example, such as a flashlight. The man-...  
WO/2000/022812A1
A number of conversion tables are stored in a computer. When a color image data is converted into the data form suited to the ink prepared for a particular printer, one corresponding to the print condition is first selected from the conv...  
WO1999055000A3
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a de...  
WO1999065026A3
A method for transferring real time information on a record carrier, typically bitstream audio on an optical disc, which method comprises encoding consecutive segments of the real time information to compressed real time data in frames, ...  
WO/2000/017744A1
A method and apparatus for expediting the processing of a plurality of instructions in a processor. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units h...  
WO/2000/013094A1
An asynchronous FIFO (226) using Asynchronous NULL Convention logic (NCL) to facilitate interfacing (224, 228) between multiple non-synchronous systems (201, 203) with a minimum of design and verification. Multiple interfaces, configurat...  
WO/2000/007093A1
The invention relates to a storage device which is arranged between at least two nodes of a data transmission system and which is provided for the purpose of carrying out a serial data transfer of binary data. The invention also relates ...  
WO1999056457A3
The present invention provides such a data transmission system (100), which encodes and transmits video, audio and text information across a global computer network without the use of a personal computer, workstation or video capture car...  
WO/2000/004543A1
A decoder (1) decodes a bit stream including a plurality of packets. Data corresponding to an access unit contains a first data part (150a-1) and a second data part (150a-2). The decoder (1) comprises a packet regenerator section (10), w...  
WO/1999/067788A1
A semiconductor memory device, which includes a FIFO from which data are read in synchronism with read clock signals (RCK). The semiconductor storage device comprises a read counter (103) for generating a first read address signal (Qn) s...  
WO/1999/066392A1
The invention proposes an apparatus for transferring data between a first device (1) and a memory area of memory means (3a; F_REG) of a second device (3), the memory area being determined by an adress (ADDR), within a system which compri...  
WO/1999/065026A2
A method for transferring real time information on a record carrier, typically bitstream audio on an optical disc, which method comprises encoding consecutive segments of the real time information to compressed real time data in frames, ...  
WO/1999/060494A1
The invention concerns a data acquisition system comprising a circuit for converting a high frequency analog input signal (a) into a plurality of digital signals (D¿1?-D¿N?, R) to be processed by a digital processing system comprising ...  
WO/1999/060495A1
The invention concerns a data acquisition system wherein a circuit for converting a high frequency analog input signal (a) into a plurality of digital signals (D¿1?-D¿N?) capable of being processed by a digital processor (8) comprises:...  
WO/1999/060475A1
A floating point multiplier unit (200) with a leading bit anticipator (240) for predicting the leading non-zero bit of the sum of carry and sum terms, the leading bit anticipator comprising an array of logic gates to provide a binary tup...  
WO/1999/060496A1
The invention concerns an analog-to-digital converter for a high frequency data acquisition system comprising a plurality of digitizers (6, 9) capable of sampling and digitizing an analog input signal (a; w1) at high frequency, the sampl...  
WO/1999/059069A1
The invention relates to a cache memory, especially for processing images. The special configuration of a memory field (CMEM), an allocation unit (MAP), a write queue (WQ), a read queue (RQ) and a data conflict recognition unit (HDET) en...  
WO/1999/059279A1
The invention manages an input buffer (111) of a coder System (110), as shown in the Figure. The contents of the buffer (111) is monitored in a monitor (133), generating an underflow signal when the buffer is empty or has an amount below...  
WO/1999/056457A2
The present invention provides such a data transmission system (100), which encodes and transmits video, audio and text information across a global computer network without the use of a personal computer, workstation or video capture car...  
WO/1999/055000A2
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a de...  
WO/1999/054812A1
An arrangement for shifting packed data is provided, in which packed data have multiple partial data each having n-byte, n being an integer greater or equal to 1. The arrangement comprises: a shifter for shifting the packed data by a pre...  
WO/1999/051021A1
A device management module (11) particularly for use in a receiver/decoder for a broadcast digital television system in which received signals are passed through a receiver to the receiver/decoder and thence to a television set. The modu...  
WO/1999/050741A1
The present invention relates to overflow protection of a buffer of a first-in-first-out type, able to store a first number $i(x) of messages from the digital module. The method is characterised by creating and sending pace messages to t...  
WO/1999/041670A1
A method of dynamically changing draining priority in a first-in/first out ('FIFO') device to prevent over-run errors is described. The method includes the steps of detecting data received in the FIFO, asserting a request to drain the FI...  
WO1999026145A3
A video graphics controller (VGC) for communicating with a frame buffer memory and a display device includes a first-in, first-out (FIFO)-configured memory, a memory controller for communicating with the frame buffer memory and controlli...  
WO/1999/036849A1
A system provides a write buffer with random access snooping capability. A random access write buffer includes a write buffer controller and a random access memory (RAM) containing a content addressable memory (CAM) address store and a r...  
WO/1999/035563A1
A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is placed on the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is...  
WO1999022302B1
A "virtual FIFO" system for use in buffering data between transacting buses (12, 18) that transfer data at different rates includes a memory device (31) and a controller (35) that partitions the memory device into multiple regions (32-1,...  

Matches 451 - 500 out of 9,225