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Patent Searching and Data


Matches 451 - 500 out of 9,270

Document Document Title
WO2001004724A3
A partitioned shift right logic circuit (300) that is programmable and contains rounding support (310a, 310b, 320a, 330a, and 330b). The circuit of the present invention accepts 32-bit value (360) and a shift amount (350) and then perfor...  
WO/2001/055834A1
A system (100) includes a first device (104) that can store and transfer data. The first device (104) is capable of transferring data at a first rate, although it may transfer data at other rates. An intermediate storage location (108) i...  
WO/2001/053943A2
A linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the linked-list...  
WO/2001/053942A2
An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algo...  
WO/2001/046988A3
The present invention comprises a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention comprises a wire pack (129) with a plurality of wires for routing a...  
WO/2001/046988A2
The present invention comprises a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention comprises a wire pack (129) with a plurality of wires for routing a...  
WO2000038063A3
A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first ident...  
WO/2001/043287A1
The present invention is a method and apparatus (106) for an N-NARY logic circuit that uses N-NARY signals (A0-A3, B0-B3). The present invention includes a shared logic tree circuit (107) that evaluates one or more N-NARY input signals a...  
WO/2001/037076A2
A system for detecting underflow and overflow errors arising within a ring buffer. When the system receives a data word to be transferred through the ring buffer, the system generates a flow indicator value to be stored with the data wor...  
WO/2001/033716A1
Non-power-of-two grey-code counters (AP1, AP4, AP5, AP6), including modulos-10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register (REG, 402, 502, 602) for storing an N-bit, e.g., 4...  
WO2000073872A3
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by...  
WO/2001/029650A1
A multiple time domain serial-to-parallel converter includes a combiner operable to receive a stream of serial data within a first time domain and to accumulate a portion of the serial data into a set of parallel data. A first hold regis...  
WO/2001/016757A1
A method is described for streaming data in Java comprising the steps of: storing audio/video data in a first addressable memory space (501); playing back the audio/video data stored in the first addressable memory space (501) when the f...  
WO/2001/009710A1
The invention relates to a method for writing and reading a buffer memory. Said buffer memory has an input for write data and an output for read data. The output of a first addressing device addresses a memory cell of the buffer memory t...  
WO/2001/009712A1
Floating-point processors (200) capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capabilities. The floating-point processor (200) includes a multiplier unit (210, 212) coupled t...  
WO/2001/006347A1
The invention concerns a stack of operands (10) for optimising the location of a storage unit and a continuous monitoring of the type of operand by the installation of a storage unit (20) recording data for each operand, said data contai...  
WO/2001/004724A2
A partitioned shift right logic circuit (300) that is programmable and contains rounding support (310a, 310b, 320a, 330a, and 330b). The circuit of the present invention accepts 32-bit value (360) and a shift amount (350) and then perfor...  
WO/2000/079378A1
A first-in first-out (FIFO) storage device for storing data including continuous identical values, which is reduced in a required circuit scale and increased in a reading operation speed, and which comprises a memory region (13) provided...  
WO/2000/077786A1
When data are transferred from a host CPU (14) to a sound processor (24) which reproduces music sounds on a real-time basis, the burden on the host CPU (14) is greatly reduced. Upon transfer of music sound data from the host CPU (14) as ...  
WO/2000/073872A2
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by...  
WO/2000/068794A1
The aim of the invention is to facilitate a secure writing of a pointer (P) that points to the respective actual data set in a cyclic memory or a circular memory such as an EEPROM. To this end, the new data set (D'#3) is written into the...  
WO/2000/068774A1
A computer system (AP1) includes a RAM-based FIFO (20) for buffering communications between a host processor (10) and a remote serial-communications device (16). The FIFO provides for quadlet, doublet, and singlet transfer widths dependi...  
WO2000022890A3
The present invention provides for a unique microchip or circuit which can, inter alia, handle both current conducting functions and man-machine-interface functions in an electrical device, for example, such as a flashlight. The man-mach...  
WO/2000/062154A1
A cyclic buffer is implemented using logical blocks corresponding to the physical blocks of the buffer. The logical blocks are mapped to the physical blocks of the cyclic buffer, and are used to create an index to the buffer. Each entry ...  
WO/2000/062153A1
The present invention relates to a buffer device of the first-in-first-out type. The buffer device comprises a data inlet In, a data outlet Out and a storage buffer MEMFIFO1. The buffer device also comprises an integrated circuit IC, whi...  
WO/2000/060749A1
An interleave/deinterleave processing in which input data is arranged and stored in a storage area having continuous addresses of a RAM (103), the stored data is read with double precision in order of address of the RAM (103) according t...  
WO/2000/057268A1
A system (20) converts data from input field types to output field types. The system (20) receives a plurality of input attributes and output attributes from an application program (10), dynamically generates a plurality of data field co...  
WO/2000/054141A1
The invention relates to a system and a method for temporary decoupling of selection, processing and elimination of data to be transmitted or received from pure transmission or reception of data telegrams of a data bus. Temporary decoupl...  
WO/2000/054163A1
An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data ...  
WO/2000/052567A1
The invention relates to a system for transmitting data records that are divided into a plurality of words between two control units (5, 20). The inventive system comprises a memory configuration having a first memory (A) and a second me...  
WO/2000/049492A1
Systems and methods for transferring very large data files to a remote location (17). The systems and methods fragment the very large data file into smaller ordered blocks using file conversion software (11a) loaded onto a computer proce...  
WO/2000/049485A1
A circuit (34) receives data asynchronously from a bus (48) on which the data is transferred on both rising and falling edges of a control signal (H-STROBE), and provides the data to an output (FIFO_DIN) synchronously with a local clock ...  
WO/2000/046949A1
To synchronize a regulary occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an ou...  
WO/2000/046661A1
The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a numb...  
WO2000038112A3
A code compaction based on macro substitutions is presented wherein the choice of possible macro substitutions is guided by an evolutionary algorithm process. In a preferred embodiment, a random population of sets of macro substitutions ...  
WO/2000/038112A2
A code compaction based on macro substitutions is presented wherein the choice of possible macro substitutions is guided by an evolutionary algorithm process. In a preferred embodiment, a random population of sets of macro substitutions ...  
WO/2000/038063A2
A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first ident...  
WO/2000/038045A1
A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains th...  
WO/2000/033166A1
Methods and apparatus for implementing a technique for determining a data rate of a serial bitstream using pattern recognition and for matching a clock speed of a deserializer to that data rate. In one implementation, a port (100) for co...  
WO/2000/022513A1
A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A-B-L+S, wherein A is the total number of bytes alloc...  
WO/2000/022890A2
The present invention provides for a unique microchip or circuit which can, $i(inter alia), handle both current conducting functions and man-machine-interface functions in an electrical device, for example, such as a flashlight. The man-...  
WO/2000/022812A1
A number of conversion tables are stored in a computer. When a color image data is converted into the data form suited to the ink prepared for a particular printer, one corresponding to the print condition is first selected from the conv...  
WO1999055000A3
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a de...  
WO1999065026A3
A method for transferring real time information on a record carrier, typically bitstream audio on an optical disc, which method comprises encoding consecutive segments of the real time information to compressed real time data in frames, ...  
WO/2000/017744A1
A method and apparatus for expediting the processing of a plurality of instructions in a processor. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units h...  
WO/2000/013094A1
An asynchronous FIFO (226) using Asynchronous NULL Convention logic (NCL) to facilitate interfacing (224, 228) between multiple non-synchronous systems (201, 203) with a minimum of design and verification. Multiple interfaces, configurat...  
WO/2000/007093A1
The invention relates to a storage device which is arranged between at least two nodes of a data transmission system and which is provided for the purpose of carrying out a serial data transfer of binary data. The invention also relates ...  
WO1999056457A3
The present invention provides such a data transmission system (100), which encodes and transmits video, audio and text information across a global computer network without the use of a personal computer, workstation or video capture car...  
WO/2000/004543A1
A decoder (1) decodes a bit stream including a plurality of packets. Data corresponding to an access unit contains a first data part (150a-1) and a second data part (150a-2). The decoder (1) comprises a packet regenerator section (10), w...  
WO/1999/067788A1
A semiconductor memory device, which includes a FIFO from which data are read in synchronism with read clock signals (RCK). The semiconductor storage device comprises a read counter (103) for generating a first read address signal (Qn) s...  

Matches 451 - 500 out of 9,270