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WO/2016/045288A1 |
Disclosed are an asynchronous FIFO controller and a method for preventing data overflow of an asynchronous FIFO buffer. The method may comprise: an asynchronous FIFO controller acquires the data volume to be acquired by a second FIFO buf...
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WO/2016/049350A1 |
Systems and methods are provided for determining identifier information associated with media content stored in a storage device; wherein the storage device comprises a plurality of clusters and stores a media file including media conten...
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WO/2016/025487A1 |
Methods for monitoring subject compliance with a prescribed treatment regimen are disclosed. In an embodiment, the method comprises measuring a drug and a metabolite level in fluid of a subject and transforming the ratio of the measured ...
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WO/2016/004629A1 |
The present invention relates to the technical field of data processing. Provided are an expected data compressibility calculation method and device. In the solution, the expected compressibility is calculated using related indicators ch...
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WO/2015/199947A1 |
Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plural...
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WO/2015/176475A1 |
A first input first output (FIFO) data buffer, the FIFO data buffer comprising: an input port, an output port, a control unit (100), a first buffer unit (101), and a second buffer unit (102); the control unit (100) is used to obtain the ...
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WO/2015/172017A1 |
Methods, systems, and apparatus, including medium-encoded computer program products, for analyzing data include: receiving data including a person's responses regarding judgments of semantic similarities between items selected from a gro...
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WO/2015/157049A2 |
Repeat-Until-Success (RUS) circuits are compiled in a Clifford+T basis by selecting a suitable cyclotomic integer approximation of a target rotation so that the rotation is approximated within a predetermined precision. The cyclotomic in...
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WO/2015/151444A1 |
[Problem] To suppress increases in the size of a fully indexable dictionary while making it possible for a target bit stream to be subjected to two types of selection operation employing the fully indexable dictionary. [Solution] An info...
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WO/2015/134103A1 |
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of ...
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WO/2015/134611A2 |
Computing systems and computer-implemented methods for specifying distributed computation (Fig. 1). The systems and methods utilize computer-readable code causing a computer to engage in reversible, self-organizing hierarchical space-lik...
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WO/2015/103676A1 |
An interface device (200) to interface a first device (400) to a second device (500). The interface device includes a first part (200) and a second part (220). The interface device (200) further includes a third part (230) to which a mem...
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WO/2015/102579A1 |
According to various aspects and embodiments, a device is provided. The device includes a memory, a Controller Area Network (CAN) controller coupled to a CAN bus, at least one processor coupled to the memory and the CAN controller. The a...
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WO/2015/069578A1 |
Multiple listlets function as a single master linked list to manage data packets across one or more banks of memory in a first-in first-out (FIFO) order, while allowing multiple push and/or pop functions to be performed per cycle. Each l...
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WO/2015/034723A1 |
An audio buffer is used to capture audio in anticipation of a user command to do so. Sensors and processor activity may be monitored, looking for indicia suggesting that the user command may be forthcoming. Upon detecting such indicia, a...
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WO/2015/021532A1 |
Embodiments of the present technology relate to data sanitization and normalization and geocoding methods that apply the same. An example method includes sanitizing geodata sets and normalizing the sanitized geodata using a normalized Le...
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WO/2015/009273A1 |
A method comprising determining an event notification associated with an event, causing rendering of the event notification to a user based, at least in part, on a determination that a notification filter indicates approval of rendering ...
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WO/2015/003245A1 |
A computing device and method are provided for converting unstructured data to structured data having a predetermined format. The computing device includes a memory storing unstructured data, an input device, a display, and a processor. ...
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WO/2014/209956A1 |
In described examples, output traffic is controlled from a buffer that stores write-miss entries (61) associated with one level of a cache for subsequent forwarding to another level of the cache (69). A determination is made about whethe...
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WO/2014/202129A1 |
The invention relates to a memory aggregation device (990) for storing a set of input data streams (902) and retrieving data to a set of output data streams (904), both the set of input data streams (902) and the set of output data strea...
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WO/2014/182314A2 |
Technologies are generally described for systems, devices and methods effective to accelerate memory access. A memory unit, including a memory and a programmable circuit, may be in communication with a processor executing a virtual machi...
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WO/2014/160925A1 |
An active feedback interface for a touch screen display that includes display of visual cues (710) to indicate when and where the display was touched by a user. The visual cues (710) may change over a period of time in accordance with a ...
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WO/2014/138894A1 |
Systems and methods for controlling branch latency within computing applications including a development framework, a visual design subsystem, and a deployment subsystem, where at runtime the deployment subsystem is operable to implement...
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WO/2014/113727A1 |
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Sw...
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WO/2014/097356A1 |
The purpose of the present invention is to reduce the processing time required for compression. A compression program executes a process on a computer, whereby, when data that appears multiple times in a file exists, data in a storage ar...
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WO/2014/097359A1 |
The purpose of the present invention is to generate compressed data that can be partially expanded while using a dynamically generated compression dictionary in a compression process. This compression program executes a process on a comp...
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WO/2014/097353A1 |
In one aspect of the present invention, a comparison process in data units that differ to data units constituting data to be compressed is suppressed with respect to data to be encoded. A compression program executes a process on a compu...
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WO/2014/070942A1 |
Communication of signals between mobile devices and automotive Controller Area Network (CAN) buses. An abstraction and communication device includes a connector, a mapping platform, and a transceiver. The connector is adapted to interfac...
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WO/2014/046930A1 |
Presented herein are techniques for detection and characterization of buffer occupancy of a buffer in a network device. Packets are received at a network device. The packets are stored in a buffer of the network device as they are proces...
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WO/2014/046742A1 |
An apparatus includes a plurality of channels (250), where each of the channels includes an asynchronous buffer (210), a latency determination block (211 ), a tap selection circuit (220), and a variable delay (202). A latency locator (21...
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WO/2014/027328A1 |
Data is written from a first domain (117) to a FIFO memory buffer (105) in a second domain(119). The first domain (117) uses a first clock signal, the second domain (119) uses a second clock signal and the memory buffer (105) uses the fi...
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WO/2014/006465A1 |
A method facilitates viewing of DICOM medical images by providing a 16-bit DICOM image on a computer readable storage medium, text-converted metadata of the DICOM image and an html-compatible conversion of the DICOM pixel data on a compu...
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WO/2014/001766A1 |
An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock ...
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WO/2014/001764A1 |
A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_s...
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WO/2014/001765A1 |
An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a freque...
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WO/2013/190690A1 |
A data predicted value generating unit (210) generates a predicted value (data predicted value) for source data (101) to be encoded on the basis of a history of the source data (101), which is floating point data. A data predicted value ...
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WO/2013/150107A1 |
The invention relates to a method for transferring data from a matrix of detector elements (D) to a memory of a data processing system by means of at least one slip ring. In said method, the data are combined in a plurality of blocks (B)...
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WO/2013/145599A1 |
For multiplexer classification for column compression of tabular data, Similar type data segments are classified into classes for grouping the data segments into compression streams associated with each one of the classes. The compressio...
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WO/2013/109683A1 |
Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry,...
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WO/2013/097393A1 |
Disclosed is a hardware abstract data structure, including a general interface (GI), a coherent interface (CI), a control and configure logic (CCL), an intelligent logic (IL) and a memory pool (MP). The GI is configured to implement the ...
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WO/2013/095337A1 |
A system and method for creating a guaranteed MSI latency by coupling a coprocessor, which may be a dedicated agent, to the existing front side bus ("FSB") in a processor (e.g., Intel® Atom™ processor) to handle deterministic interrup...
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WO/2013/091010A1 |
A method of outputting a media data sample at a media output device, comprising: receiving from a media capture device a media data sample and a timestamp associated with the received media data sample; associating the received media dat...
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WO/2013/083191A1 |
A queuing apparatus (1) having a queuing engine (2) comprising: a predetermined number, K, of queues, Q, wherein each queue Q has a number, N, of sub-queues, SQ, associated to a corresponding number, N, of input lanes of said queuing eng...
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WO/2013/049764A2 |
An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical operation is performed in response to the r...
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WO/2013/040708A1 |
In embodiments, the present invention provides method and system for determining if an existing pass log may be reused. The method may include associating an existing pass log with an encoding profile. The method may further include comp...
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WO/2013/033334A1 |
Systems and methods for adaptive bitrate streaming of alternative streams of video encoded at resolution and sample aspect ratio combinations and maximum bitrates in accordance with embodiments of the invention are disclosed. In one embo...
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WO/2013/026155A1 |
Systems and methods are provided for structuring information, including analyzing an original digital information file (DIF) to determine an information quantity (IQ) and an information value (IV). An initial manipulation process is appl...
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WO/2013/025637A1 |
According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage d...
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WO/2012/169032A1 |
The invention is a buffer apparatus provided with multiple input ports (3), multiple buffers (5) from which information input from the multiple input ports (3) is written, and at least one output port (7). The invention is provided with:...
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WO/2012/164813A1 |
Upon reading data from the main memory, an input unit (110) repeatedly starts and stops inputting the data to a compression execution unit (120) that executes lossless compression. A start address holding section (112) stores the start a...
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