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WO/2023/112571A1 |
Provided are: a semiconductor device configured to have low ON voltage, low switching loss, and to suppress high-frequency oscillation caused by noise during switching, even if the semiconductor device is made thin; and a power conversio...
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WO/2023/109219A1 |
The present application provides a transistor having a low contact resistivity and a manufacturing method therefor. The transistor comprises a substrate, a buffer layer, a channel layer, and a barrier layer which are sequentially formed....
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WO/2023/108429A1 |
The present application discloses a manufacturing method for a thin film transistor (TFT), an array substrate, and a display panel. According to the solution provided by the present application, the size and transmittance of a semi-trans...
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WO/2023/112619A1 |
[Problem] To provide a semiconductor device capable of suppressing channel current without increasing manufacturing processes and accurately forming a channel current suppression structure. [Solution] A semiconductor device 1 according t...
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WO/2023/108754A1 |
Disclosed in the present application are an array substrate and a display panel. The array substrate comprises: a substrate, a first gate electrode, a first insulating layer, a first electrode, a second gate electrode, a first conductive...
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WO/2023/112374A1 |
This nitride semiconductor device comprises: a substrate; a drift layer of a first conductivity type; a first underlayer of a second conductivity type; an intermediate high-resistance layer which has a higher resistance than the first un...
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WO/2023/112236A1 |
This semiconductor memory device has a first conductive layer, a second conductive layer, a first conductive column, a first semiconductor layer, and a first memory layer. The first conductive layer extends in a first direction. The seco...
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WO/2023/111211A1 |
The invention relates to a method for simultaneously producing high-speed (HS-npn) and high-voltage (HV-npn) SiGe hetero-bipolar transistors, by means of non-selective base deposition, the collector region of which is laterally enclosed ...
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WO/2023/108527A1 |
The present invention provides a solid-state imaging device comprising: an SOI (Silicon on Insulator) substrate comprising: a base layer; a buried oxide layer covering a part of the base layer and comprising an aperture; and an SOI layer...
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WO/2023/110457A1 |
Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment ...
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WO/2023/108785A1 |
Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, a first electrode layer, a functional layer and a second electrode lay...
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WO/2023/114583A1 |
An integrated circuit structure includes a substrate, a first device above a first section of the substrate, and a second device above a second section of the substrate. The first device includes a first source region and a first drain r...
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WO/2023/111749A1 |
A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between t...
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WO/2023/109277A1 |
The present application discloses a high electron mobility transistor structure and a manufacturing method therefor and an application thereof. The high electron mobility transistor structure comprises an epitaxial structure, a source, a...
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WO/2023/110989A1 |
The second connection region (205) is arranged above the drift layer (203), and first trenches (206) and second trenches (207) extend from the second connection region (205) into the drift layer (203), wherein the first trenches (206) an...
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WO/2023/110988A1 |
The invention relates to a method (100) for producing a power FinFET comprising two-part control electrodes, wherein: the power FinFET comprises a semiconductor body having a first connection region, a drift layer, a channel region and a...
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WO/2023/108762A1 |
Provided in the present application are a thin film transistor and a manufacturing method therefor, and a display panel. The thin film transistor comprises: a semiconductor layer; a gate electrode, which is arranged corresponding to the ...
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WO/2023/109565A1 |
The present invention provides a silicon controlled rectifier and a preparation method therefor. A first low-resistance region and a second low-resistance region are additionally provided in a first well region and a second well region o...
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WO/2023/109570A1 |
The present application provides a pseudomorphic high electron mobility transistor (PHEMT), a low-noise amplifier and a related device. The PHEMT comprises: a channel layer; a lower barrier layer and an upper barrier layer respectively p...
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WO/2023/108350A1 |
A trench field-effect transistor (FET) device (100A) includes a plurality of active trenches (102) that extends along a first axis and are distributed along a second axis perpendicular to the first axis. Each active trench (102) includes...
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WO/2023/111737A1 |
A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all- around field effect transistor device further includes an ...
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WO/2023/110101A1 |
The present disclosure relates to a Gallium Nitride, GaN, power transistor (100), comprising: a Gallium Nitride buffer layer (110) comprising a top surface and a bottom surface, the Gallium Nitride buffer layer comprising a first region ...
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WO/2023/108591A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a third nitride-based semiconductor layer, a passivation layer, a gate insulator layer, and a gate elect...
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WO/2023/108463A1 |
Disclosed in the present invention are a heterojunction transistor type light simulation synaptic device and a manufacturing method therefor. The heterojunction transistor type light simulation synaptic device comprises a channel semicon...
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WO/2023/108884A1 |
Disclosed are a nanowire/sheet device and a manufacturing method therefor, and electronic equipment comprising the nanowire/sheet device. According to embodiments, the nanowire/sheet device comprises: a substrate; a nanowire/sheet spaced...
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WO/2023/108885A1 |
Disclosed are a nanowire/sheet component having a crystal sidewall, a manufacturing method therefor, and an electronic device comprising the nanowire/sheet component. According to an embodiment, a nanowire/sheet component may comprise: a...
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WO/2023/110990A2 |
The invention relates to a method (100) for producing a power FinFET comprising two-part control electrodes, the power FinFET comprising a semiconductor body which has a second connection region and a drift layer, the second connection r...
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WO/2023/112486A1 |
In this bipolar transistor, a mesa structure including a collector layer, a base layer, and an emitter layer that are stacked on a substrate is formed. An emitter electrode electrically connected to the emitter layer is disposed on the m...
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WO/2023/102951A1 |
The present invention relates to a vertical MOSFET device and a manufacturing method therefor and the application thereof. The method comprises: forming, on a substrate, a first silicon layer, a first germanium silicon layer, a second ge...
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WO/2023/105333A1 |
A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET de...
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WO/2023/106346A1 |
Provided are: a gallium nitride layer surface treatment method with which defects in gallium nitride can be ameliorated under moderate conditions; and a semiconductor device, The gallium-nitride-layer surface treatment method comprises: ...
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WO/2023/103534A1 |
A semiconductor channel material structure is provided that has an improved, i.e., increased, effective channel area. The semiconductor channel material structure includes a plurality of semiconductor channel material nanosheets stacked ...
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WO/2023/106781A1 |
Provided is a thin film transistor. The thin film transistor comprises: a gate electrode; a spinel single-phase crystalline In-Zn-Sn oxide (IZTO) channel layer overlapping the top or bottom of the gate electrode; a gate insulating film d...
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WO/2023/102965A1 |
The invention relates to the technical field of semiconductors. Disclosed are a vertical MOSFET device and a preparation method thereof. The vertical MOSFET device comprises: a substrate; an active region, comprising a first source/drain...
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WO/2023/106001A1 |
This spintronics device generates a spin flow and comprises: a metal layer; a semiconductor layer for which the carrier mobility or the electrical conductivity is lower than the metal layer; and a gradient layer that is positioned in the...
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WO/2023/106087A1 |
The present invention suppresses a fracture mode that leads to breakage of a device in cases where a gallium nitride high-electron-mobility transistor is used as a power device. According to the present invention, a diode is connected in...
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WO/2023/106152A1 |
The present invention provides a semiconductor device which comprises: a semiconductor layer having a first main surface and a second main surface that is on the reverse side of the first main surface; an IGBT region that is formed in th...
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WO/2023/105148A1 |
The invention relates to the production of a microelectronic device, comprising: a) producing a structure with a carrier (100) provided with a semiconductor layer (12) having a first level (N1) of components, the carrier (100) being prov...
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WO/2023/102679A1 |
The present application discloses a semiconductor chip and a manufacturing method therefor, and an electronic device. The semiconductor chip comprises a substrate and a Fin FET located on the substrate; the Fin FET comprises a fin portio...
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WO/2023/106405A1 |
Provided is a compound which can be advantageously used as an organic semiconductor material and has satisfactory solubility in solvents. An organic semiconductor material including such compound is provided. An organic electronic device...
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WO/2023/103680A1 |
A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further incl...
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WO/2023/103535A1 |
Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the b...
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WO/2023/107738A2 |
A depletion-mode current source (426) having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The deple...
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WO/2023/107196A1 |
Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includ...
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WO/2023/104592A1 |
A nanosheet device is provided that has high quality epitaxially grown source/drain regions and reduced parasitic capacitance which are afforded by forming an air gap between an epitaxially grown source/drain region and a semiconductor s...
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WO/2023/103750A1 |
Stacked field effect transistors are provided such having a first power rail; a second power rail; a first Field Effect Transistor (FET) having a first gate connected to the first power rail; a second FET having a second gate connected t...
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WO/2023/105339A1 |
Provided is a semiconductor device capable of achieving a high-integrated or minute arrangement. This semiconductor device has a first transistor with a first oxide, a second transistor with a second oxide, and a third oxide. The first o...
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WO/2023/104278A1 |
A member includes a buffer layer (102) made of GaN. The member includes a source layer (104) arranged on top of the buffer layer, and the source layer is made of n-doped GaN. The member includes a first barrier layer (106A) made of AIGaN...
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WO/2023/103004A1 |
Disclosed in the present application are a driving substrate and a preparation method therefor, and a display panel. The driving substrate comprises a base, an oxide semiconductor layer, an etch stop layer and a water vapor-oxygen barrie...
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WO/2023/107106A1 |
A semiconductor device including a transistor having a threshold voltage for switching the transistor from a first conductive state to a second conductive state. The transistor includes a first region formed by a first compound semicondu...
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