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WO/2023/100454A1 |
Provided is a method for producing a silicon carbide semiconductor device, the method making is possible to suppress degradation of a built-in diode due to charging, and to suppress any variation in on-resistances of active elements. The...
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WO/2023/099112A1 |
A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets (NS) and a method of forming such a structure. The structure is a three dimensional (3D) integration by...
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WO/2023/099336A1 |
A nanosheet field-effect transistor in which the nanosheets are thinned in the source/drain regions (215), the source/drain regions of the nanosheets are wrapped by epitaxial source drain regions, and the epitaxial source/drain regions a...
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WO/2023/097445A1 |
A light-emitting substrate and a preparation method therefor, and a display device. The light-emitting substrate comprises a substrate, and a die-bonding structure, a light-shading structure and a light-emitting chip, which are arranged ...
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WO/2023/099305A1 |
Semiconductor channel layers (116) vertically aligned and stacked one on top of another, separated by a gate stack material (176) wrapping around the semiconductor channel layers, a heavily doped p-type field effect transistor (p-FET) so...
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WO/2023/093132A1 |
Provided in the present invention is a method for manufacturing an IEGT structure. The IEGT structure comprises: a substrate, on which a drift layer is formed; a first trench, which is formed in the drift layer; at least one first emitte...
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WO/2023/095396A1 |
[Problem] To reduce ON-resistance while maintaining a sufficient reverse withstand voltage in a junction barrier Schottky diode in which gallium oxide is used. [Solution] A junction barrier Schottky diode 1 is provided with: a semiconduc...
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WO/2023/092855A1 |
Disclosed are an N-polarity GaN/AlGaN-based radio frequency rectifier and a preparation method therefor. The N-polarity GaN/AlGaN-based radio frequency rectifier comprises a rectifier epitaxial wafer, an ohmic contact electrode and a SiN...
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WO/2023/096425A1 |
An Al-Sb-O-based oxide semiconductor containing aluminum (Al) and antimony (Sb) has excellent electrical conductivity and band gap, such that the semiconductor can be applied to thin film transistors and the like.
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WO/2023/092477A1 |
The embodiments of the present application relate to the technical field of semiconductors. Provided are a method for preparing a transistor, and a chip and a terminal. By means of the present application, a PN junction having a clear ju...
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WO/2023/095363A1 |
A semiconductor device 1 comprises a semiconductor layer (10) having a first main surface (10a) and a second main surface (10b), and a trench gate (30). The semiconductor layer includes an n-type drift region (12) and a p-type body regio...
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WO/2023/095391A1 |
The present disclosure pertains to a semiconductor element 1 that includes a gate electrode 2, a source electrode 3, a drain electrode 4, a semiconductor layer 5 for contacting the source electrode 3 and the drain electrode 4, and a gate...
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WO/2023/092554A1 |
A thin-film transistor and a method for preparing same, and an array substrate and a display panel. The thin-film transistor comprises: a substrate (100), and a gate electrode (101), a gate insulating layer (102), an active layer, a sour...
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WO/2023/093294A1 |
The present invention provides a gallium oxide device and a manufacturing method therefor. The gallium oxide device uses a heterogeneous substrate such as a silicon face substrate (101) to manufacture a stacked structure containing a gal...
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WO/2023/092478A1 |
The present application relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method therefor and an electronic apparatus, capable of reducing the sub-threshold swing of a transistor. T...
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WO/2023/093293A1 |
A semiconductor device and a preparation method. The semiconductor device comprises: a substrate, which has an insulation property; a first channel, which comprises a first opening formed in an upper surface of the substrate, with the fi...
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WO/2023/093248A1 |
The present invention relates to the field of surge protection devices. Disclosed are an ultra-low capacitance TVS structure having a planar structure and a preparation method therefor. The method comprises: providing a P-type substrate;...
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WO/2023/095395A1 |
[Problem] To reduce the on-resistance while ensuring a sufficient reverse breakdown voltage in a Schottky barrier diode using a gallium oxide. [Solution] A Schottky barrier diode 1 comprises: a semiconductor substrate 20 that is composed...
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WO/2023/092407A1 |
The present application relates to the technical field of microelectronics. Provided are a high electron mobility transistor, a radio frequency transistor, a power amplifier, and a method for preparing a high electron mobility transistor...
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WO/2023/096665A1 |
A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material ...
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WO/2023/092947A1 |
A manufacturing method for a self-alignment hole, and a semiconductor device. The semiconductor device comprises: a trench sidewall gate structure, comprising a gate (440) formed at the bottom of the sidewall of a trench, and an insulati...
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WO/2023/092562A1 |
The present application relates to the technical field of display, and provides a metal oxide thin film transistor, and an array substrate and a preparation method therefor. The array substrate comprises a substrate, and a drive transist...
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WO/2023/095237A1 |
According to the present invention, a buffer layer (102) is formed in a substrate (101); a barrier layer (103) that is configured from a nitride semiconductor is formed on the buffer layer (102) so that the main surface of the barrier la...
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WO/2023/095468A1 |
A high frequency integrated circuit (1) of an embodiment of the present disclosure comprises a high frequency circuit (10), a terminal (20) electrically connected to the high frequency circuit, a first transistor (M1) provided between th...
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WO/2023/095186A1 |
This magnetization rotation element comprises: a spin-orbit torque wiring; and a first ferromagnetic layer connected to the spin-orbit torque wiring, wherein the spin-orbit torque wiring has a first layer and a second layer, the first la...
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WO/2023/093249A1 |
A bidirectional TVS device having symmetrical breakdown voltages, relating to the field of ESD protection devices, and comprising an N-type substrate, an N-type buried layer, a P-type epitaxial layer, a deep trench, a P well, and N+ regi...
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WO/2023/096246A1 |
A tunneling field effect transistor having a buried drain structure is provided. The tunneling field effect transistor comprises a semiconductor pattern which is arranged on a substrate, and which has one side end portion that is thinner...
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WO/2023/092501A1 |
The present application relates to the technical field of display, and discloses a field effect thin film transistor and a manufacturing method therefor, and a display panel. The field effect thin film transistor comprises a base substra...
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WO/2023/094459A1 |
A vertical high-electron-mobility transistor, HEMT (100), comprising: a substrate (310); a drain contact (410), the drain contact being a metal contact via through said substrate; a pillar layer (500) arranged above the drain contact (41...
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WO/2023/094941A1 |
Provided is a semiconductor device capable of achieving a high-integrated or minute arrangement. The semiconductor device is provided with a first insulator, a first metal oxide, a first electrical conductor, a second electrical conducto...
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WO/2023/087808A1 |
The present invention provides a semiconductor device and a manufacturing method therefor, applicable to the field of semiconductors. The present invention provides a method for forming a double SOI (DSOI) device structure on a DSOI subs...
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WO/2023/089974A1 |
This semiconductor device comprises a lateral NDMOS transistor obtained by forming a p-type impurity region at the drain of each of a first electrostatic protection diode M21, a second electrostatic protection diode M22, and a third elec...
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WO/2023/090559A1 |
A display device according to one embodiment of the present invention comprises: a substrate; a buffer layer disposed on the substrate; a drive transistor disposed on the buffer layer and comprising a first semiconductor pattern, a first...
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WO/2022/242028A9 |
A thin film transistor and a manufacturing method therefor, an array substrate, and a display panel and device, relating to the technical field of display. The thin film transistor comprises: a gate (11) and an active layer (12) that are...
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WO/2023/091321A1 |
Systems and methods for performing hole profile modeling in a semiconductor device virtual fabrication environment are discussed. More particularly, hole profiling modeling may be performed for complicated holes used in fabricating semic...
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WO/2023/090277A1 |
[Problem] To reduce the reverse recovery time of a PN junction diode. [Solution] A semiconductor device comprising: a PN junction diode including an N-type first semiconductor region and a P-type second semiconductor region that are disp...
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WO/2023/087714A1 |
A semiconductor super-junction power device, comprising an n-type drain region (20), an n-type drift region (21) and a plurality of p-type pillars (22), wherein the plurality of p-type pillars are equal in width, and the distance between...
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WO/2023/090766A1 |
A display device and a manufacturing method therefor are provided. The display device comprises: a first semiconductor layer disposed on a substrate; a first gate insulation layer disposed on the first semiconductor layer; a first gate e...
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WO/2023/088013A1 |
The present application discloses a silicon carbide semiconductor device and a manufacturing method therefor. An epitaxial wafer comprises a semiconductor substrate; a first epitaxial layer provided on the surface of the semiconductor su...
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WO/2023/088617A1 |
Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (...
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WO/2023/090196A1 |
The purpose of the present disclosure is to provide a semiconductor device having an antioxidation metal film that is less expensive than prior-art Au films, that functions as a protective film for a metal film for soldering of a similar...
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WO/2023/088699A1 |
A semiconductor device includes a lower nano device that includes a plurality of stacked first nano sheets (120, 130), where the first nano sheets are spaced apart from each other a first distance (D1). An upper nano device that includes...
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WO/2023/088645A1 |
MULTI-VT NANOSHEET DEVICESA method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a firs...
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WO/2023/088700A1 |
An integrated circuit, IC, (1001) is provided. The IC includes a substrate (210) that includes first and second laterally adjacent channels (1002). A shared source or drain (220) region is between the first and second channels. The share...
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WO/2023/088677A1 |
A field-effect transistor device is formed with a two-dimensional material (2). The field-effect transistor device includes a channel composed of the two-dimensional material on a substrate (1) and a high-k gate dielectric (55) on the ch...
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WO/2023/090611A1 |
The present invention relates to an overpass-type semiconductor device comprising: a first gate having a fin of a predetermined height formed thereon; a charge storage layer formed on the first gate and the fin; a channel layer formed on...
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WO/2023/091546A1 |
The disclosure is directed to methods for fabricating a doped thin-film structure and devices. The device includes a substrate; and a thin-film structure disposed on the substrate. The thin-film structure includes a first region doped wi...
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WO/2023/089469A1 |
A device includes a base layer structure (705) including a first region and a second region; a first bottom gate material (704) in a plurality of first-type doped (e. g. nFET) regions in the first and second regions; a second bottom gate...
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WO/2023/091898A1 |
Advanced structures having MOSFET transistors and metal layers are disclosed. In one embodiment, a transistor structure is provided that includes a first transistor layer, a second transistor layer located under the first transistor laye...
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WO/2023/089440A1 |
Provided is a storage element provided with a new configuration. This storage element has a first electrode, a first insulating layer, a semiconductor layer, a second insulating layer, and a second electrode which are stacked, wherein th...
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