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WO/2023/104533A1 |
A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. The first CFET includes a top FET and a bottom FET. The top FET and bo...
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WO/2023/105834A1 |
Provided is a semiconductor device which has a MOS gate structure and comprises: a semiconductor substrate; a first interlayer insulating film that is provided above the upper surface of the semiconductor substrate and that has a first o...
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WO/2023/102744A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a nitride-based layer, and a plurality of gate electrodes. The second nitride-based semiconductor layer ...
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WO/2023/107420A1 |
A transistor that has a capacitance that varies in response to pressure includes a gel coupled to a gate thereof. The gel comprises a eutectic mixture having ionic conductivity.
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WO/2023/106404A1 |
The present invention provides a polymer compound that can be preferably used as an organic semiconductor material. The present invention also provides an organic semiconductor material that includes the polymer compound. The present inv...
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WO/2023/106815A1 |
The present invention relates to a vertical field effect transistor, and a manufacturing method thereof. The vertical field effect transistor according to an embodiment may include: a substrate; a source region, an insulating layer, and ...
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WO/2022/245422A9 |
A transistor device includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer incl...
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WO/2023/103536A1 |
Disclosed are an enhanced GaN HEMT radio frequency device and a manufacturing method therefor. The device comprises a substrate, a first AlN insertion layer, a GaN buffer layer, a GaN channel layer, a second AlN insertion layer, an AlGaN...
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WO/2023/105477A2 |
Electronic metadevice comprising a conductive channel; a metal layer superposed on the conductive channel; and a barrier layer located between the metal layer and the conductive channel. The metal layer includes at least one recess exten...
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WO/2023/107924A1 |
A field effect transistor includes first section and second sections. The first section includes a drift layer. A first P-well is disposed over the drift layer. A first N-source is disposed over the first P-well. A first channel is dispo...
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WO/2023/102906A1 |
The present application provides a semiconductor device and a manufacturing method therefor, and an electronic device, relates to the technical field of semiconductors, and can improve the short channel effect of a transistor. The semico...
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WO/2023/104455A1 |
A semiconductor structure is formed using a nanosheet stack that is over a semiconductor substrate. The semiconductor structure includes multiple layers of work function that surround each channel of a plurality of channels in the nanosh...
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WO/2023/097654A1 |
Disclosed in embodiments of the present application are a cold source diode, a method for manufacturing a cold source diode, and a related device, applied to the technical field of semiconductors. The cold source diode comprises a substr...
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WO/2023/097900A1 |
Disclosed in the present disclosure are a manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method comprises: providing a substrate; forming an active column on the substrate, the active...
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WO/2023/100030A1 |
A manifestation of fluid potential noise is a periodic profile characterized by a periodic saw-tooth spike in a graph of average voltage across all columns of a sensor array as a function of time. This periodic profile is indicative of a...
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WO/2023/100054A1 |
A semiconductor device including a first device that includes a plurality of nanosheets (120, 130, 140) located on top of a substrate, where the plurality of nanosheets includes first number of nanosheets. A second device that includes a...
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WO/2023/099188A1 |
Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ s...
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WO/2023/100576A1 |
This MEMS sensor comprises: a metal laminate structure which includes a first metal and a second metal different from the first metal and is provided in a portion, of a main surface of the lid-side substrate, facing an exposed portion of...
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WO/2023/098502A1 |
FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (amale portion of the female/male connection) are provided in order to connect the channels to the drain and source regi...
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WO/2023/097681A1 |
The embodiments of the present application relate to the technical field of semiconductors. Provided are a field-effect transistor and a preparation method therefor, and an electronic device, which can improve the hole mobility of channe...
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WO/2023/099316A1 |
A GAA (gate-all-around) semiconductor device includes a first source/drain region comprising an epitaxially grown first buffer layer disposed in contact with first device channel inner spacers and a device substrate, and an epitaxially g...
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WO/2023/099626A1 |
A transistor structure, includes a buffer layer (104) and a quantum well channel layer (106) on top of the buffer layer. There is a barrier layer (120) on top of the channel layer. There is a drain contact (124A, 1102A) on a channel stac...
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WO/2023/098775A1 |
In the manufacturing method for an LDMOS integrated device provided by the present invention, a provided semiconductor substrate has an NLDMOS region and a PLDMOS region; then a dielectric layer on the NLDMOS region and a dielectric laye...
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WO/2023/098600A1 |
Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nan...
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WO/2023/099134A1 |
A semiconductor structure includes a source/drain region having a top surface comprising a planar portion and at least one recessed portion. A metal contact is disposed on the source/drain region.
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WO/2023/100015A1 |
Provided is a display device having high luminance and a long service life. A display apparatus having a first layer and a second layer that is positioned above the first layer. The first layer has a substrate and a plurality of driving ...
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WO/2023/097520A1 |
The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device and an electronic apparatus, which are used for reducing the gate-drain parasitic capacitance in a semiconduc...
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WO/2023/101780A1 |
Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etch...
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WO/2023/098709A1 |
An electronic reader for electro-chemical transistors (OECT) includes a potential output control module that controls the Vd, Vs, and Vg for the OECT under test, a high accuracy current monitor module which contains a transimpedance ampl...
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WO/2023/102062A1 |
A biosensor includes a multiplexed array of electrolyte-gated functionalized field effect transistors (FET). Walls fluidically separate each of the FETs from one another provide wells corresponding to each channel of the FETS.A perimeter...
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WO/2023/100055A1 |
A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first p...
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WO/2023/098174A1 |
Provided in the present invention is an electrostatic discharge protection structure. In the electrostatic discharge protection structure, a substrate has a first conductivity type; a source region and a drain region each have a second c...
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WO/2023/101630A1 |
This invention relates to a quantum well structure containing a high mobility hole gas and a transistor device, operating in E-mode (enhancement mode), fabricated using this structure, especially; It is related to lnN/β-Ga2O3/GaN quantu...
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WO/2023/100500A1 |
A silicon carbide semiconductor device according to the present invention is provided with a silicon carbide substrate that has a first main surface; the first main surface is provided with a gate trench which extends in a first directio...
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WO/2023/099293A1 |
A semiconductor structure includes a first transistor device comprising a plurality of channel regions (208). The semiconductor structure further includes a second transistor device comprising a plurality of channel regions (224). The fi...
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WO/2023/098887A1 |
The present invention provides an AlGaN/GaN power HEMT device and a preparation method therefor. The device comprises: an n-type GaN substrate, a first p-type GaN layer, an AlGaN layer, a hole-injection-type PN junction layer and a gate ...
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WO/2023/098626A1 |
Provided in the present invention is a super-junction MOSFET device, the device comprising a plurality of cellular structures. Each of the cellular structures comprises a drain terminal electrode, an N-type drain electrode layer, an N-ty...
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WO/2023/100014A1 |
The present invention provides a high-definition display apparatus. Provided is a display apparatus comprising a transistor, a light-emitting device, a first insulation layer, a second insulation layer, and a first conductive layer. The ...
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WO/2023/100575A1 |
This nitride semiconductor device comprises: a substrate (1); a first nitride semiconductor layer (3) provided on the substrate (1); a second nitride semiconductor layer (4) that is in contact with the top of the first nitride semiconduc...
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WO/2023/100058A1 |
A transistor structure includes a source electrode (326) and a drain electrode (328) on a same plane as the source electrode. There is a channel region (208) on top of the source and drain electrodes and configured to carry a current. A ...
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WO/2023/099000A1 |
The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and...
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WO/2023/100432A1 |
This design condition computation system comprises an optimized computation unit that, using models built by a model building unit, computes a first parameter and a second parameter so that a predetermined condition is satisfied. Of the ...
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WO/2023/097662A1 |
A memory and an electronic device, which relate to the technical field of storage, and can reduce the area of a storage unit, thereby improving the storage density. The memory comprises a first transistor (T1), which is located in the pr...
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WO/2023/102369A1 |
Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a source/drain cavity and filling the cavity with a sacrificial layer. The sacrificial layer is then removed dur...
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WO/2023/099298A1 |
According to an embodiment, the semiconductor device (100) comprises a semiconductor body (1) with a first side (10) and a second side (20) opposite to the first side. The semiconductor device further comprises a first thyristor structur...
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WO/2023/098047A1 |
Provided in the present invention is a method for preparing an N-type tungsten diselenide negative-capacitance field effect transistor. The method comprises: depositing, on a gate electrode layer, a hafnium zirconium oxide ferroelectric ...
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WO/2023/100013A1 |
Provided are a semiconductor device enabling miniaturization or high-level integration, and a manufacturing method thereof. This semiconductor device includes a metal oxide, a first conductor and a second conductor on the metal oxide, a ...
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WO/2023/099115A1 |
Fork sheet FET devices with airgap isolation are provided. In one aspect, a fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet ...
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WO/2023/098343A1 |
Disclosed are a full-surrounding multi-channel drift region transverse power device and a manufacturing method therefor. The transverse power device comprises a semiconductor substrate, a buried layer, and an active region which are sequ...
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WO/2023/100012A1 |
Provided are a display device having a novel configuration and a display system having a novel configuration. This display system has a first display device capable of AR display, and a second display device. The first display device has...
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