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WO/2023/148799A1 |
A substrate has formed thereon a first semiconductor layer 1, a part of which has disposed thereon a first impurity layer 3 extending vertically, and a second semiconductor layer 4 is disposed on top of the first impurity layer. The side...
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WO/2023/148210A1 |
The invention relates to a two-dimensional electron gas field-effect transistor, referred to as TEGFET, comprising a drain (3), a source (4) and at least one channel (6) included in a heterostructure formed by a stack of at least two sem...
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WO/2023/150062A1 |
The description generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate (202), a dielectric oxide layer (204), and a field oxide region (206)....
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WO/2023/149043A1 |
This method for manufacturing a switching device (10) includes: a step for forming a source region (30) and a body region (34) in a semiconductor substrate (12) having a drift region (38); a step for forming a mask (50) that has openings...
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WO/2023/148571A1 |
Provided is a semiconductor device configured to allow miniaturization or an advanced degree of integration. This semiconductor device includes a first transistor and a second transistor on an insulating surface. The first transistor and...
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WO/2023/145256A1 |
[Problem] To further enhance driving capability regardless of the miniaturization of a fin structure. [Solution] A semiconductor device comprises: a channel layer extending from a main surface of a substrate in a direction normal to the ...
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WO/2023/145317A1 |
A semiconductor module (10) comprises: a first chip (20) that includes a main transistor (21) including an electron transit layer which serves as a main drift layer (24); a second chip (30) that includes at least a part of an active clam...
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WO/2023/145316A1 |
A semiconductor device according to the present invention comprises: a semiconductor substrate; a GaN transistor that is formed upon the semiconductor substrate and includes a drain electrode, a source electrode, and a gate electrode; an...
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WO/2023/142050A1 |
Sensing devices as well as methods of making and using the same. The sensing devices may include a pedestal (360,66,760) having a sensing element assembly (302) associated therewith and a port assembly (370,406,770) configured to mate wi...
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WO/2023/144653A1 |
Provided is a novel storage device. Provided is a storage device in which N layers (N is an integer of 2 or more) of a storage layer are stacked, the storage layer including a plurality of memory cells disposed in a matrix shape. A bit l...
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WO/2023/145497A1 |
The present invention provides a field effect transistor which comprises a base material that has a glass transition temperature of 250°C or less and an oxide semiconductor layer that is provided on the base material. The oxide semicond...
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WO/2023/146194A1 |
The present invention relates to a substrate processing device comprising: a first source supply unit for supplying a first source gas; a second source supply unit for supplying a second source gas; a first supply line for connecting the...
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WO/2023/141749A1 |
A semiconductor device having improved leakage current characteristics includes a semiconductor substrate with first and second nitride-based semiconductor layers so as to form a heterojunction therebetween with a two-dimensional electro...
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WO/2023/142393A1 |
The present invention relates to the technical field of power semiconductor devices, and relates to a high-speed flyback diode-integrated silicon carbide split gate MOSFET and a preparation method therefor. The MOSFET of the present inve...
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WO/2023/145910A1 |
Provided are a laminated structure in which there is reduced deterioration at high temperatures and which is particularly useful for power devices, a semiconductor element, and a semiconductor device. The laminated structure comprises at...
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WO/2023/145071A1 |
This semiconductor device (100) comprises a semiconductor substrate (1), a plurality of element trenches (ET), and a plurality of terminal trenches (TT). The semiconductor substrate (1) has an element region (1a) and a terminal region (1...
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WO/2023/145912A1 |
The present invention provides: a multilayer structure which is reduced in deterioration at high temperatures and is useful especially for power devices; a semiconductor element; and a semiconductor device. The present invention provides...
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WO/2023/147266A1 |
Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode tr...
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WO/2023/145805A1 |
Provided is a semiconductor device in which doping concentration peaks in a buffer region each have an apex at which the doping concentration shows a maximum, a lower tail in which the doping concentration monotonously decreases from the...
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WO/2023/143626A1 |
A semiconductor device is provided. For example, the semiconductor device can include a plurality of transistors that are arranged in an array in an X-Y plane. Each of the transistors can include a channel extending in Z direction. The s...
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WO/2023/144654A1 |
Provided is an electronic device or a semiconductor device with which it is possible to achieve miniaturization or high integration. The electronic device comprises a first electrical conductor, a second electrical conductor, a first ins...
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WO/2023/146248A1 |
The present invention relates to a thin film manufacturing method and a thin film. The thin film manufacturing method comprises: an adsorption step of adsorbing a high-k material on a substrate by spraying a source gas consisting of a hi...
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WO/2023/141993A1 |
An enhancement method for a hole linear Rashba spin-orbit coupling effect, relating to the technical field of semiconductors. The method comprises: one or more silicon atom layers are inserted into an interface on the basis of a traditio...
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WO/2023/145911A1 |
Provided are a layered structure, a semiconductor element, and a semiconductor device that are particularly useful in power devices and undergo less degradation at high temperatures. According to the present invention, a layered structur...
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WO/2023/144999A1 |
A topological insulator according to the present invention contains a first material, the electrical properties of which change in accordance with the width, while having a first region that extends in a first direction and a second regi...
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WO/2023/144652A1 |
Provided is a novel memory device. Provided is a memory device in which N (N is an integer of 2 or more) layers of memory layers that each include a plurality of memory cells formed in a matrix are laminated. Along the lamination directi...
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WO/2023/141764A1 |
A display apparatus. The display apparatus comprises a TFT substrate (11000); and a light-emitting module (1000), which is arranged on the TFT substrate (11000), wherein the light-emitting module (1000) comprises a plurality of light-emi...
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WO/2023/142540A1 |
Provided in the present application are a terminal structure, a manufacturing method and a power device. The terminal structure comprises: a first epitaxial layer; a buried layer, which is located on a side of the first epitaxial layer; ...
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WO/2023/141967A1 |
An oxide semiconductor target and thin film, a thin film transistor, and a method for improving the stability and mobility of the thin film transistor. The oxide semiconductor target comprises a matrix oxide semiconductor material and po...
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WO/2023/143921A1 |
The method comprises a step of providing a semiconductor body with a mask (3) on a top side of the semiconductor body, wherein at least one trench (2) extends from the top side into the semiconductor body. A functional portion (11) is fo...
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WO/2023/145498A1 |
A sputtering target material according to the present invention is composed of oxides containing indium (In), zinc (Zn), and tantalum (Ta) such that the atomic ratios of the respective elements satisfy all of formulae (1) to (3). (1) 0.1...
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WO/2023/140057A1 |
The purpose of the present invention is to provide an AlN single crystal substrate, a semiconductor wafer using an AlN single crystal substrate, and production methods therefore with which it is possible to produce reliable semiconductor...
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WO/2023/137851A1 |
Embodiments of the present disclosure provide a semiconductor structure and a preparation method. The semiconductor structure comprises: a stacked structure comprising a dielectric layer, an isolation layer, a metal layer, and a polycrys...
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WO/2023/138153A1 |
A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device uses, on a side surface of a field plate (FP), dielectric layers (10) having at least two different dielectric coefficients, s...
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WO/2023/137831A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor device and a preparation method therefor. The semiconductor device comprises: a substrate; a gate electrode layer, which is located on the substrate; a first cond...
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WO/2023/138933A1 |
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of sections from a top to a bottom thereof, wherein the plurality of sections has a same chemical composition and at lea...
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WO/2023/141315A1 |
Semiconductor devices with high area efficiency are described. Such a semiconductor device (200) can be positioned within an isolation structure (245), and include diodes coupled to the isolation structure (245). In this manner, the semi...
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WO/2023/139955A1 |
Provided are: a semiconductor device capable of reducing the substrate bias effect; and an imaging apparatus using the semiconductor device. The semiconductor device is provided with a first field effect transistor provided to a semicond...
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WO/2023/140356A1 |
This display device comprises a light-emitting element (230), a first transistor (210), and a second transistor (220), wherein: the first transistor includes a first gate electrode (204_1), a first insulating film (206) provided on the f...
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WO/2023/140254A1 |
Provided is a semiconductor device (100) comprising: a plurality of trench portions which are provided from an upper surface of a semiconductor substrate (10) to below a base region (14), and include a gate trench portion (G) and a dummy...
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WO/2023/137582A1 |
The present application provides a ferroelectric memory, comprising: a substrate; word lines, a source line, a bit line and a control line; and a first ferroelectric capacitor, a first transistor and a second transistor which are stacked...
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WO/2023/137927A1 |
Disclosed in the present invention are a field effect transistor having a function of mutual conversion between a logic characteristic and a storage characteristic, and a compute-in-memory chip, a circuit, and a device. The field effect ...
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WO/2023/139788A1 |
This semiconductor device comprises: a semiconductor substrate (1) formed with a material that is not gallium nitride; a buffer layer (2) formed on the semiconductor substrate (1); gallium nitride crystal regions (7) that are formed as i...
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WO/2023/139813A1 |
A chip-size-package type semiconductor device (1) that can be mounted face-down has: a semiconductor substrate (11); and a metal layer (20) that is formed on the semiconductor substrate (11) and that is exposed outside. At least one mark...
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WO/2023/140253A1 |
A semiconductor device (100) comprises: a plurality of trenches that are provided farther below a base region (14) from an upper surface of a semiconductor substrate (10), the trenches including a gate trench (G) and a dummy trench (E); ...
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WO/2023/139447A1 |
The present invention provides a semiconductor device having a transistor of very small size. The semiconductor device comprises a semiconductor layer, a first electrically conductive layer, a second electrically conductive layer, a thir...
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WO/2023/140878A1 |
A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the g...
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WO/2023/139931A1 |
Provided is a semiconductor device comprising a semiconductor substrate provided with a drift region of a first conductivity type. The semiconductor substrate has an active part and trench portions provided in the active part in the uppe...
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WO/2023/133925A1 |
The present invention provides a power semiconductor device and a manufacturing method therefor. A plurality of second resistance field plate structures which penetrate through an epitaxial layer in a first direction and extend into a su...
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WO/2023/134046A1 |
Disclosed in the present application are a novel entropy source structure based on a gate overhang modulation transistor, and a manufacturing method for said structure. The novel entropy source structure comprises a monocrystalline silic...
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