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WO/2023/131586A1 |
The present invention relates to an atomic-scale tin transistor device with ultralow power dissipation and a method for producing the same and its use.
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WO/2023/130576A1 |
Embodiments of the present disclosure provide a semiconductor device forming method and a semiconductor device. The method comprises: providing a substrate and a stacked layer structure covering the substrate, wherein the stacked layer s...
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WO/2023/130798A1 |
Disclosed in the present application are a silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET device comprises: an epitaxial wafer, which comprises a semiconductor substrate, and an epitaxial la...
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WO/2023/132231A1 |
This semiconductor device includes: a semiconductor substrate; at least one transistor that is provided on the semiconductor substrate and includes a plurality of semiconductor layers; an electrode provided to the transistor; an organic ...
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WO/2023/130502A1 |
Embodiments of the present application disclose a semiconductor structure and a fabrication method therefor. The semiconductor structure comprises: providing a substrate; forming a gate oxide layer on the substrate; and forming a gate st...
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WO/2023/122875A1 |
The present disclosure belongs to the technical field of thin film transistors. Provided in the present disclosure are a thin film transistor and a manufacturing method therefor, and a display substrate. The thin film transistor comprise...
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WO/2023/124852A1 |
The present application relates to a semiconductor structure. The semiconductor structure comprises a structure body, trench gate regions, a trench conductive region, an emitter, and a trench doped region. The structure body comprises a ...
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WO/2023/126143A1 |
Semiconductor devices and methods of forming the same include forming a buried power rail in a substrate, having a first dielectric liner of a first thickness separating the buried power rail from the substrate. An isolation structure is...
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WO/2023/122985A1 |
A driving backplane and a preparation method therefor, and a display apparatus. The preparation method for a driving backplane comprises: providing a base substrate (1), and forming a connecting layer (2a) on a side of the base substrate...
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WO/2023/126702A1 |
A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region under the gate and bet...
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WO/2023/126144A1 |
A channel fin (302) extends vertically above a bottom source/drain region (420), a protective liner (604) is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semi...
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WO/2023/123033A1 |
The present disclosure provides a display substrate, a manufacturing method therefor and a display device, comprising a base substrate; a thin film transistor located on the base substrate, wherein the thin film transistor comprises a so...
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WO/2023/127253A1 |
This semiconductor device comprises: a gate trench part provided on a semiconductor substrate; a first trench part provided on the semiconductor substrate and located adjacent to the gate trench part; an emitter region of a first electri...
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WO/2023/123378A1 |
A semiconductor device includes a first and a second nitride-based semiconductor layers, a gate electrode, and a doped nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed between the second nitride-...
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WO/2023/122863A1 |
Disclosed in the present application are an integrated circuit, a preparation method therefor, and an electronic device. The integrated circuit comprises: a substrate, and a channel layer, which is located on the substrate, wherein the s...
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WO/2023/128337A1 |
The present invention relates to a metal-semiconductor field effect transistor (MESFET) comprising: a source electrode and a drain electrode spaced apart from each other; a semiconductor layer formed on the source electrode and the drain...
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WO/2023/123374A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first nitride-based transistor, a second nitride-based transistor, and a thermal resistor. The first n...
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WO/2023/124021A1 |
The present application relates to the technical field of semiconductor power devices, and specifically discloses a semiconductor diode. The semiconductor diode comprises an n-type semiconductor layer (20); an anode metal layer (25) loca...
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WO/2023/126741A1 |
Provided is a semiconductor device that enables miniaturization and high integration. A semiconductor device having a transistor and a capacitance element, wherein: the transistor has an oxide, a first conductor and a second conductor on...
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WO/2023/123392A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a nitride-based multiple semiconductor layer, a gate electrode, a gate insulator layer, and a source electrode. The first nitride-based semiconducto...
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WO/2023/126762A1 |
A gate-all-around device is provided. The gate-all-around device includes a source/drain on a substrate, an isolation liner wrapped around the source/drain, where the isolation liner separates the source/drain from the substrate, and a o...
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WO/2023/123125A1 |
An array substrate (10), a manufacturing method for the array substrate (10), a display panel (30), and a display apparatus, belonging to the technical field of display. The array substrate (10) comprises a base substrate (11) and a driv...
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WO/2023/127520A1 |
A nitride semiconductor device 1 includes: a low-resistance Si substrate 2 having a first main surface 2a and a second main surface 2b opposite thereto; a high-resistance Si layer 3 that is formed on the first main surface 2a and that ha...
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WO/2023/125202A1 |
Disclosed in embodiments of the present invention is a semiconductor device, comprising multiple sources, multiple gates, and multiple drains located in an active area. In the active area, the sources, the gates, and the drains are arran...
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WO/2023/124246A1 |
The present application relates to the technical field of semiconductors, and provides a lateral field-effect transistor and a preparation method therefor. In the lateral field-effect transistor, a gate pad and a source pad, which are ar...
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WO/2023/124670A1 |
The present application relates to a method for preparing an LDMOS device, and the LDMOS device. The method for preparing the LDMOS device comprises the steps of: forming a drift region of a first conductivity type; forming a buried laye...
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WO/2023/125145A1 |
The present invention provides a DMOS device having a junction field plate and a manufacturing method therefor. A drain area is located at a surface of a semiconductor substrate, a source area is located in the semiconductor substrate at...
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WO/2023/127023A1 |
This silicon carbide semiconductor device comprises: a gate trench (91) that is formed in a semiconductor layer (1) and penetrates through a source region (40) and a body region (30) to reach a drift layer (20); and a Schottky trench (92...
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WO/2023/123564A1 |
The present invention relates to semiconductor devices. Disclosed is a current protection-type semiconductor device. The internal resistance of the device may be instantaneously changed from a low resistance to a high resistance when an ...
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WO/2023/123363A1 |
A nitride-based bidirectional switching device is for working with a battery protection controller having a power input terminal, a discharge over-current protection (DO) terminal, a charge over-current protection (CO) terminal, a voltag...
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WO/2023/125013A1 |
The present invention relates to a semiconductor device and a preparation method therefor. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and the size...
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WO/2023/127255A1 |
Provided is a semiconductor device provided with a gate trench portion, and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising: a first conductive-type drift region provided in a semiconductor...
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WO/2023/124902A1 |
The present invention relates to a trench DMOS device and a manufacturing method therefor. The trench DMOS device comprises an extended gate layer provided on the inner surface of a gate insulation layer; and the extended gate layer comp...
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WO/2023/129293A1 |
A semiconductor device having a substrate (18) and an orthorhombic polar crystalline oxide k-Al203 layer (24) epitaxially and heterogeneously integrated above a wurtzite single-crystal Group III-Nitride layer (22) comprising AlN disposed...
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WO/2023/127187A1 |
This nitride semiconductor device comprises: a substrate; a drift layer; a first high-resistance semiconductor layer; a p-type nitride semiconductor layer; a second high-resistance semiconductor layer; a gate opening portion reaching the...
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WO/2023/122901A1 |
The present application relates to the technical field of semiconductors. Provided are a semiconductor device and a manufacturing method therefor, and an electronic device. By means of the present application, an equivalent oxide thickne...
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WO/2023/127795A1 |
[Problem] To provide an information processing device and a signal conversion method having a high degree of freedom in disposition locations of electrodes. [Solution] One aspect of the present invention provides an information processin...
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WO/2023/125894A1 |
A cold-source Schottky transistor and a preparation process therefor. The cold-source Schottky transistor comprises a substrate (101), a source region, a drain region (4), a channel region (3), a source electrode, a drain electrode and a...
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WO/2023/125487A1 |
The invention provides an optical tweezer apparatus, comprising: a first electrode; a second electrode; a transistor array located between the first and second electrodes, the transistor array being composed of transistors distributed in...
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WO/2023/123559A1 |
Provided are a graphene-loaded noble metal composite powder and a preparation method therefor, and a Schottky device. Graphene oxide and a noble metal precursor are used as raw materials, and the composite powder is prepared by means of ...
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WO/2023/122876A1 |
The present invention relates to the technical field of thin film transistors, and provides a thin film transistor and a manufacturing method therefor, and a display substrate. The thin film transistor comprises: a base substrate; and a ...
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WO/2023/126714A1 |
The present invention provides a semiconductor device which has a large ON-state electric current. A transistor of the semiconductor device comprises: a first insulator; a first semiconductor layer on the first transistor; a second semic...
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WO/2023/121819A1 |
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack...
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WO/2023/121794A1 |
Integrated circuit structures having a metal gate plug landed on a dielectric dummy fin, and methods of fabricating integrated circuit structures having a metal gate plug landed on a dielectric dummy fin, are described. For example, an i...
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WO/2023/119955A1 |
Provided are: a semiconductor device in which the lateral diffusion of impurities is suppressed; a method for manufacturing the same; and an imaging device using the semiconductor device. The semiconductor device comprises: a semiconduct...
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WO/2023/119833A1 |
Provided is an antenna module suitable for use in a signal frequency band from several tens of GHz to 100 GHz or more.　The antenna module includes a substrate in which at least the uppermost surface is a single crystal of silicon carbi...
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WO/2023/120815A1 |
A SiC semiconductor device having high pressure resistance properties is disclosed. The present invention provides a SiC semiconductor device comprising: a SiC substrate having a first surface and a second surface; an insulating area for...
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WO/2023/116875A1 |
Embodiments of the present invention discloses an epitaxial structure of a semiconductor device, a preparation method therefor, and a semiconductor device. The epitaxial structure comprises a substrate, a nucleation layer and a buffer la...
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WO/2023/121799A1 |
Integrated circuit structures having a buried power rail are described. In an example, an integrated circuit structure includes a device layer including a drain structure having an uppermost surface. A buried power rail is within the dev...
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WO/2023/116357A1 |
A semiconductor device (100), comprising: a substrate (110); a first-conductivity-type buried layer (120), which is arranged in the substrate (110); a drift region (142), which is arranged on the buried layer (120); a drain region (130),...
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