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WO/2023/175437A1 |
The present invention provides a semiconductor device which has a high degree of integration. A semiconductor device according to the present invention comprises first and second transistors and an insulating layer. The first transistor ...
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WO/2023/173679A1 |
Embodiments of the present disclosure provide a transistor and a manufacturing method therefor, a memory, and an electronic device. The transistor comprises: a source layer; a semiconductor layer; a drain layer, wherein the source layer,...
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WO/2023/176887A1 |
Provided is a semiconductor device comprising: a first conductive drift region provided in a semiconductor substrate having a front surface and a back surface; and a first conductive buffer region provided closer to the back surface of t...
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WO/2023/176082A1 |
Provided is a MEMS sensor comprising a semiconductor substrate, a sensor portion formed on the semiconductor substrate, a pad portion formed on the semiconductor substrate, and a connection wire which is formed on the semiconductor subst...
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WO/2023/173914A1 |
Disclosed in the embodiments of the present application is a vertical channel transistor structure. Contact layers are respectively introduced between a source electrode and a dielectric layer and between a drain electrode and the dielec...
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WO/2023/176891A1 |
A gate electrode (51) is disposed in a different position from an electric field relaxation layer (40) in the normal direction, and an electrode (73) for an electric field relaxation layer is disposed on an interlayer insulating film (60...
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WO/2023/173425A1 |
Embodiments of the present application provide a structure of and a preparation method for a silicon carbide transistor. The structure of the silicon carbide transistor comprises: a silicon carbide substrate, a first element being doped ...
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WO/2023/175792A1 |
The present invention comprises: a p layer 1 that extends in a direction horizontal to a substrate 20, at a position away from the substrate; an n+ layer 2 that serves as a first impurity layer and that is located on one side of the p la...
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WO/2023/175820A1 |
The present invention provides a method for producing a semiconductor device, the method comprising: a step in which a first insulating film (20) that has a first opening (20a) is formed; a step in which a first resist (24) that has a se...
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WO/2023/176907A1 |
Provided is a semiconductor device that comprises: a base region of a second conductivity type that is disposed between a drift region and an upper surface of a semiconductor substrate; a first lifetime region that is disposed in a drift...
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WO/2023/176150A1 |
In the present invention, a pixel transistor is positioned in a pixel-separating trench of a solid-state imaging device. The solid-state imaging device comprises the trench and the pixel transistor. The trench separates the pixels. The...
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WO/2023/176759A1 |
[Problem] To provide: a layered structure having excellent crystallinity; a semiconductor device; and a manufacturing method by which such structure and device can be obtained in an industrially advantageous manner. [Solution] In the pre...
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WO/2023/176591A1 |
A sintered body of an oxide containing an In element, a Ga element, and an Al element, wherein the atomic compositional ratio of the In element and the Al element satisfies formula (1) and formula (2). [In]/([In]+[Ga]+[Al])>0.70 … (1...
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WO/2023/176744A1 |
The present invention relates to a GaN epitaxial substrate comprising: a GaN substrate; and a GaN buffer layer epitaxially grown on the GaN substrate, wherein: the GaN epitaxial substrate includes a point A that exists in the GaN substra...
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WO/2023/173507A1 |
A TFT substrate and a manufacturing method therefor, a liquid crystal display panel, and an OLED display panel. A source electrode (61) and a drain electrode (62) of the TFT substrate are both obtained by etching a conductive layer (50)....
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WO/2023/176932A1 |
This semiconductor device comprises a semiconductor substrate of a first conductivity type, a semiconductor layer of the first conductivity type, a first electrode, a second electrode, a first trench, a second trench, an insulating layer...
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WO/2023/173335A1 |
Provided in the present application are a silicon carbide power device and a preparation method therefor, and a power conversion module. The silicon carbide power device comprises a silicon carbide substrate, an epitaxial layer and an oh...
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WO/2023/175436A1 |
The present invention provides a semiconductor device which comprises a transistor of a very small size. A semiconductor device according to the present invention comprises a transistor, a first insulating layer and a second insulating l...
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WO/2023/176260A1 |
This semiconductor device (100) comprises a substrate (101), a buffer layer (102), an intermediate layer (103), an electron transport layer (104), an electron supply layer (105), a source electrode (201) and drain electrode (202), and a ...
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WO/2023/176056A1 |
A semiconductor device (1A) according to the present invention comprises: a chip (2) which has a main surface (3); a first inorganic film (27) which contains an insulator and covers the main surface; a second inorganic film (41) which co...
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WO/2023/174610A1 |
In at least one embodiment, the method is for producing a power semiconductor device (1) and comprises the following steps: - providing a semiconductor body (2) based on SiC, - irradiating at least a first portion (21) of a top side (20)...
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WO/2023/168749A1 |
Provided in the present application are an array substrate and a display panel. The display panel comprises an array substrate. An ion implantation barrier layer in the array substrate and at least part of a channel portion of an active ...
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WO/2023/170270A1 |
The present invention relates to a ceramic substrate comprising: aluminum oxide (AI2O3) with an average grain size between 1.31 and 1.55 μm; Zirconium dioxide (ZrO2) with an average grain size between 0.65 and 0.75 μm, Yttrium oxide (Y...
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WO/2023/168897A1 |
Provided in the present disclosure are a semiconductor structure and a preparation method therefor. The preparation method for a semiconductor structure provided by the present disclosure comprises the following steps: providing a substr...
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WO/2023/171137A1 |
This semiconductor device comprises a vertical field effect transistor having a low impurity concentration layer (33), a body area (18), a gate trench (17) that extends in a first direction parallel to the top surface of the low impurity...
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WO/2023/168752A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory and a manufacturing method therefor. The semiconductor structure comprises at least one transistor. The...
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WO/2023/171454A1 |
This semiconductor device includes: a semiconductor layer that has a surface; a source region and a drain region that are positioned on the surface, separated in a first direction, as viewed from the thickness direction which is perpendi...
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WO/2023/168807A1 |
The embodiments of the present disclosure provide a semiconductor structure and a method of forming same. The semiconductor structure comprises: a gate dielectric layer; and a gate electrode located on a surface of the gate dielectric la...
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WO/2023/168570A1 |
A method for partially forming dielectric isolation for a gate-all-around device, the method comprising: providing a substrate (101), and forming a fin structure and a surrounding stacked member (104) on the substrate (101), the surround...
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WO/2023/170511A1 |
A semiconductor device having a high storage density is applied in the present invention. The semiconductor device includes a first insulator, a first layer, a second insulator, a second layer, a third insulator, and a third layer layere...
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WO/2023/170782A1 |
In the present invention, a first insulating layer 21 is provided on a substrate 20. Separate from the insulating layer are: a plurality of first impurity layers n+ layers 2 set apart in the horizontal direction and vertical direction wi...
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WO/2023/171134A1 |
[Problem] To provide a semiconductor device that has a structure suited for miniaturization and that is capable of achieving high-voltage resistance. [Solution] A semiconductor device comprises: an SJ layer which extends in a first direc...
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WO/2023/170732A1 |
The purpose of the present invention is to provide a plasma processing method which is highly controllable and is capable of selectively removing a metal-containing layer. The purpose is achieved by a plasma processing method that plasma...
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WO/2023/171438A1 |
This nitride semiconductor device comprises: an electron supply layer; a gate layer; a gate electrode; a passivation layer; a source electrode; a drain electrode; an active region; and an inactive region that is adjacent to the active re...
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WO/2023/171502A1 |
Corrosion resistance, oxidation resistance, and high-temperature strength are secured for a semiconductor substrate of SiC, while also achieving a reduction in production costs, by: forming a molding 20 by layering a paste comprising SiC...
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WO/2023/172794A1 |
Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include...
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WO/2023/172279A1 |
A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming fi...
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WO/2023/170755A1 |
In the present invention, a memory device comprises a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in plan view, said memory device controlling the voltage applied to a first ga...
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WO/2023/172578A1 |
A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the ch...
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WO/2023/169592A1 |
Provided are a MOSFET device and a manufacturing method therefor. An embodiment comprises: first forming a first implant area which is easy to diffuse, and then sequentially forming a second implant area which is not easy to diffuse and ...
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WO/2023/171147A1 |
Provided is a semiconductor device in which it is possible to suppress both short channel and variations in transistor characteristics. This semiconductor device comprises a semiconductor substrate and a field effect transistor provided ...
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WO/2023/171139A1 |
This semiconductor device comprises: a semiconductor layer having a first surface and a second surface on the opposite side from the first surface; a bottom gate region of a first conductivity type formed in the semiconductor layer; and ...
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WO/2023/172280A1 |
A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removin...
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WO/2023/171402A1 |
A storage device (500) according to an embodiment of the present disclosure comprises: a first memory (501) that allows data reading/writing; a second memory (502) that allows data reading/writing; a detection unit (504) that detects mag...
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WO/2023/171431A1 |
A detection device provided with: a substrate; a plurality of photodiodes, which are arranged on the substrate and in each of which a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and an upper electrode a...
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WO/2023/170738A1 |
This magnetization rotating element comprises a spin-orbit torque wire and a first ferromagnetic layer connected to the spin-orbit torque wire, wherein the spin-orbit torque wire includes an amorphous structure, and the amorphous structu...
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WO/2023/171138A1 |
[Problem] To provide a semiconductor device which makes it possible to improve withstand voltage performance while having a further compact structure. [Solution] A semiconductor device comprising: a source region that is of a first condu...
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WO/2023/166827A1 |
A semiconductor device according to the present invention comprises: a semiconductor chip that has a first main surface; a withstand voltage holding structure that is formed in the peripheral region in the periphery of an element formati...
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WO/2023/168138A1 |
Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate...
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WO/2023/164911A1 |
Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact cou...
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