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WO/2022/196303A1 |
This delay circuit 100A includes a plurality of delay stages STG connected in multiple stages, wherein at least one of the delay stages is a first delay unit 110A. Gates of a first P-type transistor MP1 and a first N-type transistor MN1 ...
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WO/2022/190997A1 |
A delay adjustment circuit according to the present disclosure comprises: a plurality of delay adjustment units which are connected in series and which each include one or more first delay elements (102) that delay an input signal on the...
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WO/2022/191014A1 |
The light source driving circuit pertaining to the present disclosure comprises a first delay circuit (10) that imparts a delay at a first time resolution on the basis of a clock signal to an inputted signal, and a second delay circuit (...
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WO/2022/190517A1 |
Proposed is a distance sensor that transmits a transmission pulse signal without using a clock signal. A transmission circuit 30 comprises a comparator 31, a comparator 32, a voltage control circuit 33, and an AND circuit 34. The compara...
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WO/2022/186998A1 |
A delay element (300) including a first set of field effect transistors, FETs (M1N), with gates configured to receive a first control voltage (VBP); a second set of FETs (/MSN) coupled in series with the first set of FETs (M1N) between a...
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WO/2022/187175A1 |
An integrated circuit (130) includes first and second bus terminals, a pass-gate transistor (QI), first and rising time accelerator (RTA) control circuits (201, 203), and first and second falling time accelerator (FTA) control circuits (...
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WO/2022/181479A1 |
The present invention comprises: a switching element (10) that has a first terminal (D1), a second terminal (S1), and a control terminal (G1) for controlling current flowing between the first terminal (D1) and the second terminal (S1), t...
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WO/2022/175050A1 |
The invention relates to a level converter (L) for adjusting a first reference potential (P1) and/or a first communication voltage (K1) of a first component (E1) to a second reference potential (P2) and/or a second communication voltage ...
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WO/2022/175068A1 |
MULTIPHASE SIGNAL GENERATORAn apparatus which includes a multiphase signal generator circuit. The multiphase signal generator circuit is configured to receive as input a complementary analog signal having a fundamental frequency, and gen...
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WO/2022/169518A1 |
A method for achieving a first uniformity level in a processing rate across a surface of a substrate is described. The method includes receiving the first uniformity level to be achieved across the surface of the substrate and identifyin...
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WO/2022/150188A1 |
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does no...
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WO/2022/137821A1 |
The present invention reduces the size of a circuit in an SAR ADC in which a circuit for cancelling ripples is provided. According to the present invention, a digital-analog converter generates at least one of a pair of analog signals ...
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WO/2022/137993A1 |
A connection circuit (30) connected between a first amplifier circuit (10) and second amplifier circuit (20) includes: a first switch (31) connected between another current terminal of a third transistor (13) and the second amplifier cir...
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WO/2022/136695A1 |
A method of determining a detection pattern signal is described wherein the method comprises: receiving a base clock signal and an analog detector signal at a clock cycle of the clock signal, wherein the analog detector signal may compri...
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WO/2022/127290A1 |
A signal correction circuit and a server. The circuit comprises: a first signal processing module (1) receiving an input signal and positive and negative power supply voltages, generating a first control voltage, controlling an input sig...
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WO/2022/131924A1 |
A method of generating pulses for controlling an optical device is described comprising: receiving a clock signal and one or more logical pulse selection signals (314), wherein the timing quality of the clock signal, preferably the timin...
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WO/2022/121539A1 |
The present application discloses a synchronization machine and a synchronization system, the synchronization machine comprising: a power distribution module and a shaping module which are connected to each other, the power distribution ...
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WO/2022/114685A1 |
The present invention relates to a clock distribution apparatus, and a signal processing apparatus and an image display apparatus which comprise same. The clock distribution apparatus according to an embodiment of the present invention c...
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WO/2022/115650A1 |
A circuit and method are described for generating a low-jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing th...
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WO/2022/110697A1 |
A control circuit and a delay circuit. The control circuit comprises: a control unit (41), a first feedback unit (42) and a second feedback unit (43). The first feedback unit (42) outputs a first feedback signal according to the voltage ...
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WO/2022/109364A1 |
One example includes a glitch filter system (100). The system (100) includes an input stage (102) to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-e...
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WO/2022/108862A1 |
Described embodiments include a comparator circuit (400) comprising an input voltage terminal (310), a reference voltage terminal (312), and a rising edge decode circuit having inputs coupled to the input voltage terminal and the referen...
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WO/2022/106960A1 |
In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a contro...
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WO/2022/102901A1 |
A signal generation method according to the present specification may comprise the steps of: generating a plurality of first control pulses of a first group by using a plurality of first delayed clocks; and generating a plurality of seco...
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WO/2022/102002A1 |
Provided is an A/D conversion circuit with which it is possible to eliminate an offset error without increasing the layout area or the consumed current, even when a memory-cell-overwriting comparator is used. A sequential-comparison an...
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WO/2022/102334A1 |
A data reception device of the present disclosure comprises: a first phase adjustment circuit that adjusts a phase between a plurality of data signals received via a plurality of data signal lines; and a second phase adjustment circuit t...
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WO/2022/094521A1 |
Certain aspects of the present disclosure generally relate to circuitry and techniques for digital -to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally include...
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WO/2022/089080A1 |
Disclosed are a method and apparatus for performing threshold correction on a comparator, and a system. The method comprises: reading an initial level which is output by a comparator after a reference value, which is received by means of...
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WO/2022/088748A1 |
Provided are a clock generation circuit, a memory, and a clock duty cycle calibration method. The clock generation circuit comprises: an oscillation circuit (101), which is used for generating a first oscillation signal (OSC+) and a seco...
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WO/2022/088749A1 |
Provided in embodiments of the present application are a calibration circuit, a memory, and a calibration method. The calibration circuit comprises: a differential input circuit which is used to receive a first oscillating signal and a s...
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WO/2022/093344A1 |
Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system f...
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WO/2022/064893A1 |
This DLL circuit (110) comprises a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stopping circuit (116). The phase delay circuit (114) generates a plurality of delay signals having respectiv...
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WO/2022/060483A1 |
One embodiment is a baseline restoration ("BLR") circuit for a photo-counting computed tomography ("PCCT") signal chain, the BLR circuit comprising a comparator for comparing a shaper voltage output from a shaper component of the PCCT si...
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WO/2022/059068A1 |
A comparator circuit (5) outputs digital signals (XQP, XQN) corresponding to differential signals (IN, /IN) to a flip-flop (3) having a prescribed prohibition input. A conversion circuit (4) differentially amplifies the differential sign...
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WO/2022/057316A1 |
The present application provides a delay circuit and a delay structure. The circuit comprises: a first delay unit used for delaying rising and/or falling edges of a pulse signal and having an input end that receives the pulse signal and ...
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WO/2022/053521A1 |
An electronic device (200) comprises a synchronisation system (2) that receives a signal (6) clocked by a first clock signal (50) having a first frequency and receives a second clock signal (52) having said first frequency, but offset in...
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WO/2022/055087A1 |
A signal delay device disclosed in this specification may be configured by comprising: a delay circuit for outputting a delayed feedback signal by delaying a delay start signal by means of a plurality of unit delay units connected in ser...
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WO/2022/052705A1 |
A non-linear calibration method for a phase interpolator, comprising: outputting a first sampling clock, causing an edge of the first sampling clock to align with an edge of a reference clock; outputting a third sampling clock, causing a...
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WO/2022/055881A1 |
Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in ...
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WO/2022/044809A1 |
This imaging device comprises: light-receiving pixels; a reference signal generation unit; a first amplification unit that is connected to a first power source node and a second power source node, performs a comparison operation on the b...
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WO/2022/045106A1 |
A differential amplification circuit (110) generates a first current (I1) and a second current (I2) that have a current difference that is the result of amplifying the voltage difference between an input voltage (Vin) and a reference vol...
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WO/2022/038885A1 |
The present invention increases the degree of freedom of design in a solid-state imaging element having a logic gate in a comparator. A comparison circuit compares an input potential that has been input with a predetermined reference p...
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WO/2022/038148A1 |
The invention relates to a device (1) for detecting alternating voltage, comprising input terminals (2) for the application of an alternating voltage (Vin) to be detected and output terminals (3), at which application of the alternating ...
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WO/2022/033006A1 |
The embodiments of the present application relate to a comparator, comprising: a first-stage circuit, which is used to receive a voltage signal to be compared and a reference voltage signal Vref, and generate and output a first amplifica...
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WO/2022/026108A1 |
Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage ...
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WO/2022/025861A1 |
This document describes systems and techniques for adaptive frequency control in integrated circuits (202). In response to operating conditions that permit a lower frequency (322) of a clock signal (306), the described systems and techni...
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WO/2022/023042A1 |
An electrical pulse generating device (100) is disclosed, which is connected or connectable to a load (90). The electrical pulse generating device comprises an electrical energy storage module (40), and a power supply (30), which is conf...
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WO/2022/018560A1 |
Provided is a semiconductor device having reduced power consumption. This semiconductor device has a differential circuit and a latch circuit, wherein the differential circuit has a transistor including an oxide semiconductor in a channe...
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WO/2022/015549A1 |
Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only fre...
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WO/2022/014412A1 |
[Problem] To provide an imaging device that, when a comparison is made between an analog pixel signal and a predetermined reference signal, can suppress an error of a reverse timing of the comparison result. [Solution] The imaging device...
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