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WO/2024/082252A1 |
A pulse synchronization control method for a converter, and a converter and a computer-readable storage medium, which relate to the technical field of converters. In the method, a pulse modulation instruction is sent to each power module...
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WO/2024/081461A1 |
A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive ...
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WO/2024/080571A1 |
A clock phase calibration device according to one embodiment of the present disclosure comprises: a clock generation module for generating a plurality of clocks on the basis of a reference clock; a clock sampling module for sampling sign...
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WO/2024/077818A1 |
Provided in the embodiments of the present application are a voltage-controlled frequency circuit and related products. In the voltage-controlled frequency circuit, a clock generation circuit generates a clock oscillation signal accordin...
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WO/2024/076866A1 |
A synthesizable clock doubler is disclosed. The clock doubler is implemented using unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing...
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WO/2024/076489A2 |
A voltage comparator includes a boosting circuit that is configured to boost a direct current (DC) bias of the comparator. The boosting circuit includes transistors that are different in size, a larger one of the transistors being config...
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WO/2024/076898A1 |
A pulse-shaping network configured for use in a radio frequency (rf) power amplifier system, the pulse-shaping network comprising: a coupled magnetic element comprising a first inductive element magnetically coupled to a second inductive...
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WO/2024/069428A1 |
A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase con...
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WO/2024/069368A1 |
A system includes an inverter including: a first galvanic isolator separating a low voltage area from a high voltage area, the first galvanic isolator having a first galvanic isolator output path; a second galvanic isolator having a seco...
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WO/2024/060478A1 |
The embodiments of the present disclosure disclose a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit comprises a first signal path and a second signal path. The first signal path is configured to ...
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WO/2024/064455A1 |
A system includes a receiver. The receiver includes an input stage having an input and an output, and a first resistor coupled between the output of the input stage and the input of the input stage. The receiver also includes an output s...
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WO/2024/059368A1 |
A phase interpolator includes a sampling circuit configured to capture samples of an output of the phase interpolator, a delay circuit configured to delay sampling by the sampling circuit, a comparator configured to provide a comparison ...
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WO/2024/055578A1 |
Disclosed in the present invention are a pulse power amplification method and a standard cell. The key points of the technical solution are that: according to the present invention, a light amplification by stimulated emission of radiati...
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WO/2024/052063A1 |
A signal generating circuit (1100) comprising a series of cascade elements (1103a, 1103b), each comprising a cascade input, a cascade output; a clock input, a reset element (1115, 1117), and a first switch (1105a, 1107a) and a second swi...
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WO/2024/046990A1 |
Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction cir...
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WO/2024/045269A1 |
A data sampling circuit, a data receiving circuit, and a memory. The data sampling circuit comprises: a comparison circuit and an adjustable driving circuit, wherein the comparison circuit is configured to receive first data, second data...
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WO/2024/049715A1 |
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can ...
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WO/2024/043985A1 |
A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a vol...
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WO/2024/041931A1 |
A device comprises a voltage-mode filter circuit, a current-mode output circuit, and a regulation circuit. The voltage-mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current-mode output ...
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WO/2024/037157A1 |
An adjustable time delay circuit. The circuit comprises: a first adjustment module, comprising a first input end and a control output end; a second adjustment module, comprising a second input end and a first output end; a third adjustme...
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WO/2024/035989A1 |
A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that ou...
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WO/2024/032136A1 |
Disclosed in embodiments of the present disclosure are an offset calibration circuit and a memory. The offset calibration circuit comprises an adjustable delay circuit, a phase detection circuit and a phase adjustment control circuit. Th...
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WO/2024/023164A1 |
A comparator (10) comprises an input stage (IS), configured to receive a pair of input signals (S1, S2) to generate at least one differential current signal (S3). The comparator (10) further comprises an output stage (OS) configured to g...
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WO/2024/017795A1 |
Proposed is a method for reduced-bounce switching of an electromechanical switching element that comprises multiple contacts and an armature, characterized in that, in a first step, a specified number of switching operations are performe...
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WO/2024/014642A1 |
A pulse width modulation (PWM) control device for electronic pre-charging of a battery pack is provided. The PWM control device for electronic pre-charging of a battery pack according to an embodiment of the present invention is a PWM co...
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WO/2024/015304A1 |
A radiofrequency (RF) power amplifier for a plasma processing system includes a switching transistor having a drain terminal, a source terminal, and a gate. The source terminal is connected to a reference ground potential. The RF power a...
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WO/2024/006590A1 |
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock...
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WO/2024/006589A1 |
One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal g...
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WO/2023/246567A1 |
Provided are a timing conversion device and method capable of precisely realizing signal timing delay by means of a simple structure, a write leveling system and a computer readable medium. The timing conversion device comprises a time-t...
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WO/2023/249788A1 |
An aspect relates to a glitch absorbing buffer (GABUF) including: a delay element configured to delay an input signal by a delay to generate a delayed input signal; and a logic circuit, responsive to the input signal, the delayed input s...
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WO/2023/245749A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/250007A1 |
A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors ...
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WO/2023/240703A1 |
A voltage test circuit and a voltage test method. The voltage test circuit comprises: a threshold setting module (11), which is provided with a first input end, a second input end and a power supply end, wherein the first input end is us...
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WO/2023/231461A1 |
Embodiments of the present application provide a chip, comprising: a pulse detection circuit, a filter circuit and an output circuit. The pulse detection circuit is used for acquiring an input signal, determining a first output signal ac...
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WO/2023/235164A1 |
In certain aspects, an apparatus (110) includes a first gating circuit (420) having an input (422) and an output (426), wherein the input of the first gating circuit is configured to receive a first clock signal (Clk-sw). The apparatus a...
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WO/2023/234059A1 |
A phase synchronization circuit according to one embodiment of the present disclosure comprises: a signal generation unit that has a plurality of delay units connected in series, and can output a first signal resulting from delaying an i...
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WO/2023/231120A1 |
Disclosed in the present application are a square wave shaping circuit and a display panel. In the present application, a control module controls, on the basis of the current between the control module and a second power supply signal ac...
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WO/2023/232625A1 |
In a clock signal generator (10) for generating a reference signal (144) and a clock signal (142) for a plurality of microwave signal generators, in particular microwave solid state power amplifier modules, the clock signal generator has...
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WO/2023/223468A1 |
This bias voltage generation circuit comprises: a first constant current source for supplying a first constant current; a second constant current source for supplying a second constant current that is smaller than the first constant curr...
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WO/2023/221252A1 |
Disclosed in the present invention is a pulse voltage generation apparatus having an adjustable pulse width. The apparatus comprises: a switch control circuit, which is used for generating a control signal; a clock generation circuit, wh...
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WO/2023/221230A1 |
Disclosed in embodiments of the present disclosure are a time delay circuit and a memory. The time delay circuit comprises: a self-shielding module and a time delay module. The self-shielding module is configured to receive an initial co...
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WO/2023/224866A1 |
A comparator circuit with a speed control element is disclosed herein. The speed control element may include a variable voltage source and one or more transistors. Using a voltage supplied by the variable voltage source, the one or more ...
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WO/2023/216171A1 |
A clock buffer circuit (1000). The clock buffer circuit (1000) comprises a loop oscillator (1100); the loop oscillator (1100) comprises an input end for receiving a first clock signal, an output end for outputting a second clock signal, ...
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WO/2023/206656A1 |
A clock generation circuit, an equidistant four-phase signal generation method, and a memory. The clock generation circuit comprises: a four-phase clock generation circuit (801), which is used for receiving an internal clock signal and a...
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WO/2023/205150A1 |
A synchronization module is configured to generate a synchronization signal for transmission to at least one of a power generator and/or at least one match network, wherein the synchronization signal is formed with pulses having varying ...
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WO/2023/196653A1 |
A noise tolerant buffer circuit, configured to interface a controller to a switching device, that includes an input, a first buffer, a second buffer, an output, and a switching device. The input provides a control signal to the first buf...
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WO/2023/194644A1 |
A microelectronic circuit may comprise at least one timing event detector circuit configured to generate a timing event observation signal as a response to a change in a digital value at an input of an associated register circuit during ...
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WO/2023/184851A1 |
A duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, a counting unit uses a counting clock signal having a clock signal frequency higher than that of a correction clock sig...
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WO/2023/178819A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular relates to a comparator circuit, a mismatch correction method, and a memory. The comparator circuit comprises: a first transistor, one termina...
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WO/2023/183708A1 |
In certain aspects, an apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an ...
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