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WO/2017/052899A1 |
Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first vari...
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WO/2017/053019A1 |
A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillat...
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WO/2017/045338A1 |
An automatic frequency band calibration method for rapid lock of a phase-locked loop system. An AFC module is used to calibrate the frequency band of a VCO, and automatically select a frequency band according to a target frequency point,...
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WO/2017/043254A1 |
This phase synchronization circuit is provided with: a detection unit that detects transition of an input clock signal; an oscillation unit that generates a clock signal having a frequency corresponding to a first control signal and chan...
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WO/2017/034702A1 |
Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to ...
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WO/2017/030755A1 |
Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a fi...
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WO/2017/030849A2 |
Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode...
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WO/2017/027132A1 |
In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages...
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WO/2017/023688A1 |
Embodiments include a hybrid frequency synthesizer comprising a direct digital synthesizer configured to generate a digital output signal having a frequency determined by an input signal received from an externally-generated signal sourc...
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WO/2017/019365A1 |
Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry (100) is made simpler ...
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WO/2017/007522A1 |
Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code (306) or a crossing PI code (308) in a clock and data recovery (CDR) circuit (206) until one or more preset criteria are s...
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WO/2017/006339A2 |
A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultan...
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WO/2017/000886A2 |
A low dropout linear regulator, a method for increasing stability thereof and a phase-locked loop. The low dropout linear regulator comprises a reference voltage source (201), an error amplifier (202), a regulating circuit (203), a load ...
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WO/2017/000672A1 |
A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the refe...
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WO/2017/002437A1 |
An FPGA portion 21 connected to an oscillator 31 which outputs a first clock is provided with: a PLL circuit 22 which outputs a second clock having a frequency that is a certain proportion of the frequency of the first clock, and which o...
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WO/2017/000885A1 |
Disclosed are a coarse adjustment unit array applied to a digital controlled oscillator and related apparatuses. The coarse adjustment unit array applied to a digital controlled oscillator comprises a number X of coarse adjustment units;...
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WO/2016/209463A1 |
A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclic...
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WO/2016/209287A1 |
Systems and methods are provided in which an offset phase-locked loop (PLL) system can be configured as part of a radio frequency transmitter. The PLL can include a phase detection circuit including a first input configured to receive an...
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WO/2016/209289A1 |
Systems and methods are provided in which a voltage-controlled oscillator for a radio transmitter includes a LC tank circuit, and a muting circuit. The LC tank circuit includes an inductive element and a capacitive element; wherein the i...
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WO/2016/207758A1 |
A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the...
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WO/2016/206337A1 |
A circuit, configuring local oscillator signals, comprises: a local oscillator signal generation circuit (11) and a local oscillator signal control circuit (12), wherein the local oscillator signal generation circuit (11) is configured t...
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WO/2016/202368A1 |
A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed. The quadrature phase detector comprises a first circuit arran...
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WO/2016/204935A1 |
A dual-band voltage controlled oscillator (VCO) includes: a first oscillator circuit including a first inductor; a second oscillator circuit including a second inductor; a first mode switch configured to electrically connect or disconnec...
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WO/2016/204961A1 |
Phase compensation in an I/O (input/output) circuit includes a triangular control contour with a simplified generation circuit. A linear control circuit can generate a digital N-bit linear count, and route the least significant M bits [(...
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WO/2016/202367A1 |
An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a ...
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WO/2016/204962A1 |
Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for bet...
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WO/2016/198116A1 |
A phase locked loop arrangement (1) beamformingcomprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump curre...
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WO/2016/197364A1 |
A method and system for real-time calculating the dynamic phase shift signal. The method comprises the following steps: segmenting the medium frequency signals in the testing channel and the reference channel, respectively; reading out t...
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WO/2016/193549A1 |
In a RFID sensor tag, a sensing element (25) is connected to an oscillator 23 such that an oscillation frequency (fOSC) of the oscillator (23) is dependent on a value of a predetermined variable sensed by the sensing element (25). The os...
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WO/2016/192836A1 |
The invention relates to a phase-locked loop for generating a frequency-stabilized, mostly high-frequency signal featuring a new type of fully automatic adjustment of individual parameters of the loop in order to optimize the stability o...
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WO/2016/195898A1 |
A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the delay added to the feedback signal to align a leading edge transition in the f...
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WO/2016/196848A1 |
A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a d...
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WO/2016/197113A1 |
In described examples, a frequency detection technique includes generating first and second signals such that a frequency of the first signal is the same as a frequency of the second signal and such that the second signal is phase-shifte...
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WO/2016/188008A1 |
An apparatus and method for improving the long term stability of a crystal oscillator. The apparatus comprises: an oven-controlled crystal oscillator (1), a frequency divider (2), a phase discriminator (3), a reference voltage source (4)...
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WO/2015/163988A9 |
Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter conv...
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WO/2016/186756A1 |
A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be a...
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WO/2016/179789A1 |
Embodiments relate to a voltage oscillator (VCO) (100) that uses a replica bias circuit (103) to generate a cascode bias voltage. The VCO (100) generates an output periodic signal having a frequency and phase that is less or not suscepti...
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WO/2016/177406A1 |
The present invention relates to a signal processing device having channel list update function, the update function, when called, effecting updating of the channel list in a substantially reduced amount of time. More particularly, the p...
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WO/2016/172920A1 |
Disclosed is an automatic alignment envelope tracking power amplifier configuration. The envelope tracking power amplifier configuration adds an sequentially connected input signal envelope detector, envelope generation module and automa...
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WO/2016/173614A1 |
A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shi...
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WO/2016/175249A1 |
The objective of the present invention is to resolve the problem that at the high-frequencies at which MR elements oscillate, the peak width of an oscillation spectrum is wide, and to provide a high-frequency phase-locked oscillator circ...
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WO/2016/176205A1 |
In an example, a phase-locked loop (PLL) circuit (108) includes an error detector (202) operable to generate an error signal; an oscillator (204) operable to provide an output signal having an output frequency based on the error signal a...
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WO/2016/171827A1 |
A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path (203) coupled to a first node (204), wherein the supply bias path provides a charging bias current to th...
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WO/2016/170932A1 |
The purpose of the present invention is to obtain a frequency synchronization device capable of frequency synchronization between modules without using a GPS signal. This frequency synchronization device is provided with: a voltage-contr...
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WO/2016/167283A1 |
A fine adjustment synthesizer 1 comprises a fractional phase-locked loop having a reference integer divider 6, a phase comparator 7, a loop filter 8, a variable frequency oscillator 9, a mixer 4, a band pass filter 13, and a feedback pat...
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WO/2016/161504A1 |
Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating c...
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WO/2016/155278A1 |
A circuit and equipment for quickly locking a microwave frequency source, comprising a sampling phase detector (PD), a loop filter (LF), a preset circuit module, a frequency divider (1/N) and a voltage-controlled oscillator (VCO), wherei...
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WO/2016/155279A1 |
A low-phase noise microwave frequency source circuit and equipment, and a method. The low-phase noise microwave frequency source circuit comprises a sampling phase discriminator, a clamping circuit module, a loop filter and a voltage-con...
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WO/2016/160145A1 |
Systems and methods are disclosed that may determine phase offsets in wireless devices. In accordance with some embodiments, a phase of a local oscillator signal associated with transmission of data from a wireless device may be measured...
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WO/2016/150471A1 |
The programmable frequency control system presented herein provides frequency programmability and phase noise reduction for signals generated by a plurality of frequency programmable phase-locked loops (PLLs). In general, a modulated dat...
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