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WO/2016/153810A1 |
A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase inp...
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WO/2016/150182A1 |
A time-to-digital converter in a phase-locked loop which can improve the phase-locked precision. The time-to-digital converter comprises a delay unit (301) which inputs a first signal and a sampling unit (302) which inputs a second signa...
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WO/2016/153653A1 |
A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a...
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WO/2016/147729A1 |
[Problem] To provide a DDS that is configured by including many digital components and has improved resolution. [Solution] A DDS 52 is provided with an NCO 23, a ΔΣ modulation unit 28, and a BPF 29. The NCO 23 outputs a digital signal....
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WO/2016/144486A1 |
In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit conf...
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WO/2016/138706A1 |
Disclosed is a clock switching method. The clock switching method comprises the following steps: receiving a selection instruction, and acquiring a selection signal value; if the selection signal value is a first preset value, then gatin...
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WO/2016/137622A1 |
Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage curren...
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WO/2016/134524A1 |
Clock and data recovery (CDR) systems for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal are provided. A phase detector receives the local clock signal and the...
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WO/2016/130255A1 |
A method and apparatus for charging a crystal oscillator are provided. A voltage generating module outputs a ramp voltage signal to a ring oscillator. The ring oscillator generates and outputs a waveform based on the ramp voltage signal....
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WO/2016/130251A1 |
A charge pump including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit in...
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WO/2016/130258A1 |
An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through t...
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WO/2016/119139A1 |
A circuitry (20) for providing an oscillating output signal (CLK) in connection with an integrated circuit chip (200) is provided. The circuitry (20) includes a crystal (CR) off the chip, and an oscillator circuitry on the chip for elect...
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WO/2016/120503A1 |
The invention relates to a synchronisation system and a method for an electrical generator unit coupled to an electrical energy system, for facilitating the synchronisation between the electrical generator unit and the electrical energy ...
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WO/2016/122341A1 |
A digital system of measuring parameters of the signal (phase, frequency and frequency derivative) received in additive mixture with Gaussian noise. The system is based on the use of variables of a PLL for calculating preliminary esti...
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WO/2016/119835A1 |
A sub-sampling phase-locked loop (100) is described, which comprises a digital-to-time converter (102), a sampler module (104), an interpolator (106), and a voltage controlled oscillator (108). The digital-to-time converter (102) is conf...
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WO/2016/118183A1 |
The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of disc...
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WO/2016/118931A1 |
A signal generator that provides signals for multiple outputs is presented. In some embodiments, a signal generator can include switching circuitry that is coupled to provide a signal to an active output of a plurality of outputs in resp...
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WO/2016/118936A1 |
A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase...
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WO/2016/115114A1 |
An integrated circuit including a phase detector; a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and th...
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WO/2016/115430A1 |
Embodiments of a microwave oscillator and method for amplitude noise reduction are generally described herein. The oscillator may include a resonator and an RF bridge to combine an incident and a reflected RF signal. The oscillator may f...
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WO/2016/112719A1 |
Provided is a temperature sensor integrated in an RFID label, comprising a temperature control oscillator, a numerical control oscillator, and a phase detector; the output terminal of the temperature control oscillator is connected to th...
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WO/2016/111793A1 |
A method for controlling an electronically actuated valve is described. An ignition signal for a combustion engine is received. The ignition signal is filtered. A control pulse for controlling an electronically actuated valve is generate...
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WO/2016/109923A1 |
Disclosed is a method and a radio network node for compensating for local oscillator pulling or pushing. The method comprises determining, in a digital domain, a correction phase for the local oscillator to offset a phase error caused by...
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WO/2016/109815A1 |
In described examples of a method of frequency estimation, a clock output from a frequency synthesizer (110) is received at an input of a ring encoder (121). The ring encoder (121) generates outputs, including a ring encoder output clock...
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WO/2016/104464A1 |
[Problem] To shrink circuit scale and to reduce power consumption. [Solution] A phase digital converter is provided with a counter for counting the number of cycles of a first signal, a first phase difference detector for generating a ph...
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WO/2016/101836A1 |
A clock delay method and device, a delay phase locked loop and a digital clock management unit. The clock delay method comprises: step 1, delaying an input clock for Ti through a delay line (44), so as to obtain an output clock; step 2, ...
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WO/2016/097332A1 |
Coherent spectroscopic methods are described, to measure the total phase difference during an extended interrogation interval between the signal delivered by a local oscillator (10) and that given by a quantum system (QS). According to o...
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WO/2016/095679A1 |
A digital fractional frequency phase-locked loop (PLL) control method and the PLL, the PLL comprising: a control apparatus, a time-digital converter (TDC), a digital loop filter (DLF), a digital control oscillator (DCO), a feedback divid...
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WO/2016/097700A1 |
A variable frequency divider arrangement is arranged to divide a frequency of an incoming signal by a variable number D to provide a resultant signal. The arrangement comprises: a first counter (108) having a first clock input and a firs...
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WO/2016/097412A1 |
A wideband digital phase meter is described together with a technique for phase detection. The device measures the phase difference between 2 signals and is suitable for integration into a single MMIC. The input signals are compared digi...
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WO/2016/096853A1 |
The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference ...
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WO/2016/097707A1 |
A phase locked loop comprises: a controllable oscillator (102); a variable divider arrangement (108, 110) which takes a signal from the controllable oscillator (102) and divides it by a variable amount to provide a lower frequency signal...
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WO/2016/093004A1 |
[Problem] The present invention addresses the problem of the accumulation of quantization errors during holdover control, when a reference signal cannot be acquired, in a standard signal generating device provided with a synchronizing ci...
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WO/2016/076419A1 |
This phase measuring device is provided with: a first AD converter 2 for digitizing a first periodic input signal X at each predetermined sampling timing, and outputting the digitized signal as a digital signal Xd; a first zero crossing ...
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WO/2016/072600A1 |
A delay line-based time-to-digital converter according to an embodiment of the present invention comprises: a coarse counter for counting pulses of a timing clock so as to measure the time when an edge of an input signal is detected; a f...
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WO/2016/073120A1 |
Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in- phase and quadrature clock signals and produces four clock outputs at a phase ...
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WO/2016/072023A1 |
Provided is a semiconductor integrated circuit that includes: a phase-locked loop circuit (300) that outputs a clock signal; an internal circuit (311) that performs processing; electrical capacitances (701-703); and switch circuits (904-...
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WO/2016/067942A1 |
The invention is provided with: a subject information detection unit A101 that detects a pulsation signal based on vascular pulse wave information from a subject; and a signal processing section A16 that normalizes the pulsation signal.
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WO/2016/067014A1 |
A digitally controlled voltage controlled oscillator comprising an Nbit digital to analogue convertor arranged to receive a frequency change demand signal as a digital Nbit word, and having an output provided via an integrator to a volta...
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WO/2016/064535A1 |
Method and apparatus for signal sampling timing drift compensation are provided. Raw time values or deviations between clock and data are measured and filtered to generate filtered time information, and the filtered time information is c...
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WO/2016/063700A1 |
This phase synchronization circuit is provided with: a reference phase generation circuit for sequentially generating a reference phase value; an oscillation circuit for generating a first clock on the basis of a difference between the r...
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WO/2016/061781A1 |
Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type...
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WO/2016/059089A1 |
The invention relates to a phase detection method (200), comprising the following steps: receiving (201) a receiving sequence (Yj) of values (Y0, Y1, YN-1) of a receiving signal (Y) that are scanned at a known scanning frequency fs, wher...
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WO/2016/059088A1 |
The invention relates to a phase detection method (200), comprising the following steps: receiving a plurality of consecutive values of a receiving signal (Y) having a known scanning frequency fS as a response to a transmitting signal ha...
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WO/2016/061057A1 |
A primary ion source subassembly for use with a secondary ion mass spectrometer may include a unitary graphite ionizer tube and reservoir base. A primary ion source may include a capillary insert defining an ionizer aperture. An ionizer ...
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WO/2016/057289A1 |
Various aspects of this disclosure comprise systems and methods for synchronizing sensor data acquisition and/or output. For example, various aspects of this disclosure provide for achieving a desired level of timing accuracy in a MEMS s...
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WO/2016/057883A2 |
In described examples, an FLL (frequency locked loop) oscillator/clock generator (100) includes a free-running oscillator (110), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched c...
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WO/2016/056389A1 |
Provided is a frequency synthesizer capable of high-speed switching and having few unwanted frequency components in the output frequency signal. In this frequency synthesizer (1), a direct digital synthesizer (DDS) (2) operating on the b...
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WO/2016/050211A1 |
A high-frequency delay-locked loop and a clock processing method for the high-frequency delay-locked loop. The high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, and a pu...
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WO/2016/054614A1 |
A novel and useful 60 GHz frequency generator based on a third harmonic extraction technique which improves system level efficiency and performance. The frequency generator employs a third harmonic boosting technique to increase the thir...
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