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Matches 1 - 50 out of 31,720

Document Document Title
WO/2021/079563A1
A fractional phase-locked loop that multiplies the frequency of a reference signal by a non-integer and outputs a resultant signal to an output unit, comprises: a first frequency adjusting unit which controls the frequency of a signal to...  
WO/2021/077246A1
A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multip...  
WO/2021/080105A1
An apparatus for time synchronization of a relay apparatus, according to an embodiment of the present invention, comprises: a downlink reception unit for transmitting a downlink signal and a downlink transmission unit for forming a downl...  
WO/2021/076255A1
Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a...  
WO/2021/076685A1
In some embodiments, a molecular clock includes: a waveguide gas cell containing gas molecules having a rotational spectral line with a first frequency; a voltage-controlled oscillator (VCO) to generate a clock signal; a transmitter refe...  
WO/2021/068131A1
The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency wi...  
WO/2021/068326A1
Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, wherein the phase-lock acceleration circuit comprises a pulse width extraction control circuit and a current in...  
WO/2016/043592A8
A phase-domain delta-sigma (ΔΣ) modulator in a phase digitizer determines a demodulated phase error based on a phase-modulated frequency signal, in which a carrier frequency is modulated with a fundamental frequency and an associated p...  
WO/2021/035229A3
Embodiments of the disclosure provide a voltage / frequency modulation (VFM) system for determining a baseline voltage and a programmable ring oscillator (PRO) code for various dynamic voltage frequency scaling (DVFS) set points. The VFM...  
WO/2021/060787A1
Disclosed is an electronic device that is configured to determine whether a phase locked loop (PLL) circuit is operating normally, thereby preventing component damage in the electronic device and preventing disconnection from a communica...  
WO/2021/061575A1
A method and apparatus for enhancing the stability of an oscillator circuit by generating a comb of frequencies in a non-linear resonator member in response to a drive frequency, the oscillator circuit including a voltage controlled osci...  
WO/2021/055155A1
A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an ...  
WO/2021/047758A1
A time difference determining device determines a time difference between a first digital signal and a second digital signal. It comprises a first time difference determining branch, comprising a first delay line, in turn comprising N fi...  
WO/2021/049423A1
This atomic resonator 10 comprises: a gas cell 1 in which alkali metal atoms have been enclosed; a light detection device 2 that detects light that has traversed the gas cell 1 and converts said light into an electric signal; a high freq...  
WO/2021/042266A1
An asynchronous sampling architecture (100) and a chip. The asynchronous sampling architecture (100) is used for receiving a first input data string (dl) from the opposite end, and comprises: a first register (102) used for caching the f...  
WO/2021/036274A1
Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, wherein same belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises:...  
WO/2021/036518A1
Disclosed is a fast-locking phase-locked loop circuit for avoiding a cycle slip, wherein same belongs to the technical field of integrated circuits. The fast-locking phase-locked loop circuit comprises: a phase frequency detector, a char...  
WO/2021/036805A1
A signal generation circuit, a signal generation method, a digital time conversion circuit and a digital time conversion method. The signal generation circuit comprises: a first generation circuit configured to generate a periodic first ...  
WO/2021/036775A1
A signal generation circuit, a signal generation method, a digital-to-time conversion circuit, and a digital-to-time conversion method. The signal generation circuit comprises: a first generation circuit configured to generate a periodic...  
WO/2021/035166A1
A temperature insensitive oscillator system. The system includes a substrate having a first surface and an opposing second surface, a CMOS device with one or more CMOS circuits attached to the first surface of the substrate, one or more ...  
WO/2021/029959A1
A method and corresponding system of determining a property of a particle, comprising: flowing the particle in a device comprising a suspended microchannel resonator, the suspended microchannel resonator comprising a microfluidic channel...  
WO/2021/026658A1
An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mod...  
WO/2021/026657A1
A delay device includes a tuning network including first and second tuning components having frequency responses that overlap in an intermediate frequency band to provide a group delay response. A delay modifier is in communication with ...  
WO/2021/024619A1
Provided is an atomic cell glass that can make it difficult for a change in oscillation frequency to occur over time in an atomic oscillator. This atomic cell glass is a glass for use in atomic cells, and has a density of 2.4 g/cm3 or ...  
WO/2021/025820A1
Phase variations between a transmitter (TX) waveform and a receiver (RX) waveform produced by a TX Phase-Locked-Loop (PLL) and a RX PLL, respectively, is a source of error in processing delay calibration used, e.g., in Round Trip Time (R...  
WO/2021/024345A1
A first phase adjuster (11) adjusts the phase of either a first or second AC voltage (V1, V2) generated in a negative resistance circuit (10), such that the shift amount φ in a first variable phase shifter (12) is kept within the range ...  
WO/2021/021250A1
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other bene...  
WO/2021/016740A1
Disclosed are a single-phase adaptive phase-locked apparatus and method. The single-phase adaptive phase-locked apparatus comprises: a phase detector, a proportional-integral controller, a dynamic wave trap, and a voltage-controlled osci...  
WO/2021/021704A1
A device (100) includes a clock generator (106) configured to generate a root clock signal (MCLK) based on an input clock signal (CLK) and a clock generator divider integer setting. The device (100) also includes a first component (112A)...  
WO/2021/016085A1
Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part o...  
WO/2021/011270A1
Apparatus, methods, and computer-readable media for facilitating beam-based sequence spaces for synchronization signals are disclosed herein. An example method for wireless communication for a first device includes selecting a subset of ...  
WO/2021/011830A1
Methods, devices and systems for providing accurate measurements of timing errors using optical techniques are described. An example timing measurement device includes an optical hybrid that receives two optical pulse trains and produces...  
WO/2021/011955A1
A system, circuit (750, 1550) and method (1700) for providing a controlled oscillator frequency with reduced phase noise for use in a communication system. In one embodiment, the circuit (750, 1550) includes a delay line (775, 1575) coup...  
WO/2021/002988A1
A device includes a physical medium attachment (PMA) (110), a physical coding sublayer (PCS) (120), a phase detector (140), and an oscillator (150). The PMA (110) receives data (102) at a first speed and overclocks the received data to a...  
WO/2021/000751A1
The present disclosure provides a phase-locked loop circuit, a configuration method therefor, and a communication apparatus. The phase-locked loop circuit comprises: a phase-locked loop main circuit; and a phase temperature compensation ...  
WO/2020/258419A1
A temperature detection device comprising: a temperature-sensitive clock circuit (1), a temperature-sensitive signal generating module (2), a sampling clock generating module (3), and a sampling module (4). The temperature-sensitive cloc...  
WO/2020/256849A1
Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines...  
WO/2020/254090A1
The invention relates to a temperature-controlled RF resonator (200) comprising a thermally insulating enclosure (110) inside which the following are implemented: - at least one resonating element (120) configured to deliver an RF output...  
WO/2020/251709A1
Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a...  
WO/2020/246092A1
Provided is a phase synchronization circuit constituted by a digital circuit, wherein a circuit for generating phase difference information is reduced in terms of circuit scale. A multiphase clock generation circuit generates a plurali...  
WO/2020/244158A1
A fractional divider in modulated phase-lock loop circuits. The fractional divider can receive a base dividing value having integer and fractional components, and can also receive a data signal to modulate the dividing value. A shift val...  
WO/2020/247144A1
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine at least one of an orthogonal frequency division multiplexing (OFDM) parameter associated with the...  
WO/2020/243494A1
A plasma generation system and method includes connected solid state generator modules. The solid state generators can be connected to a shared reference clock to generator an output, and/or can be combined using a phase optimization tec...  
WO/2020/237690A1
A phase synchronization apparatus, a phase synchronization system and a transceiving apparatus, which are used to provide, to each radio-frequency transceiver chip in a multi-chip splicing scheme, a local oscillation signal with a consis...  
WO/2020/243414A1
Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in po...  
WO/2020/240341A1
Provided is a semiconductor device that shows less temperature dependency. According to the present invention, a switched capacitor is constructed with a second transistor, a third transistor, and a second capacitance. The second and thi...  
WO/2020/232726A1
The present application relates to the technical field of chips, and provides a phase locked loop, capable of solving the problems of high power consumption and high noise when a charge pump has non-ideal characteristics and complicated ...  
WO/2020/220714A1
A phase-locked loop circuit comprises a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for output...  
WO/2020/220341A1
Provided are a semiconductor device and an electronic apparatus. The semiconductor device comprises a bare chip, and an oscillator and a blocking cover arranged in the bare chip, wherein the oscillator comprises a resonant cavity; the re...  
WO/2020/223547A1
A nanoelectromechanical systems (NEMS) oscillator network and methods for its operation are disclosed. The NEMS oscillator network includes one or more network inputs configured to receive one or more input signals. The NEMS oscillator n...  

Matches 1 - 50 out of 31,720