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JP2730819B2 |
PURPOSE: To stably decode CMI data into NRZ data. CONSTITUTION: Whenever rise transition is generated in CMI data, an inter-pulse transition time interval output part 3 generates a pulse RTP based on a pulse from a clock generation part ...
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JPH10503355A |
An encoding system uses a modified 8/9 rate modulation code to encode 8-bit data symbols into 9-bit cells in a conventional manner in accordance with the modified code and 9-bit ECC symbols into 10-bit cells by (i) encoding 8 bits of the...
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JP2723828B2 |
PURPOSE: To continuously switch serial data between an NRZ system and an SPL system so as to transmit them with the minimum load of a CPU. CONSTITUTION: CPU 10 writes transmission data into a FIFO memory part 30 as NRZ system parallel da...
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JP2725058B2 |
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JPH1065916A |
To prevent the linearity between image data and a pulse width even when the pulse width is made narrower and to prevent a density change at a highlight part of an output image from being unnatural. A triangle wave generating section 108 ...
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JP2721781B2 |
A method and apparatus for generating high rate run length limited trellis codes and increasing minimum distance between output sequences of partial response channels with constrained channel inputs without requiring codes with spectral ...
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JP2718168B2 |
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JP2718183B2 |
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JPH1051315A |
To perform bit reduction (band compression) by using an approximate waveform by the synthesis of a prescribed substitutive impulse waveform. This system is provided with frame memories 1 and 5, difference signal detection parts 2 and 6, ...
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JP2715891B2 |
PURPOSE: To reduce the functional burden of a multiplexer by switching a system from an active system to a standby system based on the selection information of a node device from a user's line terminating device. CONSTITUTION: Based on a...
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JP2716140B2 |
A code converter includes: extraction means (31) for extracting a reference level from a binary-coded input signal, which is offset at the predetermined voltage level and varies arbitrarily with the same polarity as the voltage level; tw...
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JP2712502B2 |
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JP2715074B2 |
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JP2712353B2 |
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JP2709778B2 |
PURPOSE: To perform high-speed processing for replacing positive digital data outputted from a microprocessor or the like and negative digital data expressed by the complementary of '2' with a pulse duration converting signal accompanyin...
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JP2705939B2 |
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JP2560648Y2 |
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JP2701789B2 |
PURPOSE: To optimize the operation of the circuit without substantially increasing the number of components and to lower the manufacture cost by making the width of a phase skip narrow by making least transmitting circuit alterations. CO...
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JPH1013236A |
To reduce the circuit scale of a D/A(digital/analog) conversion device by performing both the FIR filter processing and noise shaping processing, after an inversion of the digital voice signals in the D/A conversion. An inverter 2 invert...
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JPH1013237A |
To provide a wireless communication method capable of being effectively applied to a battery-driven radio equipment or the like and sufficiently securing security. In this wireless communication method, in the case of conducting data tra...
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JP2691138B2 |
PURPOSE: To reduce EMI radiation by converting data to be put on a plurality of data lines in such a mode that the EMI generated from the data lines are reduced as compared with the case where the data are not converted. CONSTITUTION: Wh...
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JPH09326704A |
To obtain a multi-value record coding method suitable for a recording and reproducing method where a mutli-value signal is reproduced depending on the amplitude of a reproduction signal by coded multi-value signals under the restriction ...
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JPH09312641A |
To provide the symbol synchronization circuit in which fast synchronization locking is attained and which is realized with a simple configuration in the case of demodulating symbol data from input data whose one symbol is represented by ...
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JP2681400B2 |
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JP2681401B2 |
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JP2681399B2 |
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JP2679385B2 |
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JP2679493B2 |
PURPOSE: To generate a synchronization clock synchronously with a frequency of a transmission speed of reception data at a fast lock time with no adjustment. CONSTITUTION: A synchronization pulse generating circuit 3 generates synchroniz...
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JP2677297B2 |
A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the valu...
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JP2675621B2 |
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JP2674554B2 |
PURPOSE: To obtain an optical transmission system which may occupies a narrow band as an equalized amplifying circuit and is sufficiently tolerant of mark rate variation by converting an NRZ code received signal into a differential equal...
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JP2674119B2 |
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JP2673068B2 |
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JPH09288864A |
To inhibit a digital data from being easily duplicated. The data is divided into a symbol sequence 100 and formed into blocks in a module 102, where error detecting/correcting symbols 104 are added and also a header and a synchronization...
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JP2668901B2 |
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JP2664848B2 |
Apparatus and methods are provided for encoding a predefined number of bits of binary data into codewords having a predefined number of bits for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device ...
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JP2664249B2 |
Clock timing is extracted from N level, multilevel codes of megabits per second data by determining a baud clock among the N-1 possible clocks synchronized to all the level cross points. A discriminator is used with a clock and if correc...
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JP2662398B2 |
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JPH09246952A |
To provide a small-sized analog/digital converter operated at a high speed with less power consumption. This circuit capable of forming a core element for the analog/ digital converter and a multivalue/binary value converter circuit is p...
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JPH09246974A |
To encode picture control signals to picture element clock signals by providing an encoding circuit for positioning a second transition inside at least one clock cycle to the variable position of a first transition in response to control...
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JPH09246976A |
To provide a ternary judgement circuit for not causing ternary judgement errors even when noise provided with large waviness is added to reception signals in the ternary judgement circuit provided in the reception part of a communication...
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JPH09246973A |
To improve the efficiency of data communication by PWM modulation and to shorten communication time. A conversion table preparation part 12 checks the distribution of data compression-encoded in a compression-encoding part 11 and prepare...
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JP2653642B2 |
PURPOSE: To prevent a PLL loop gain from being sensitively chanted by a data bit pattern by providing a phase comparison gain limiter and avoiding gain limit of a phase comparator within a range of a transition occurrence frequency from ...
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JPH09232958A |
To provide a DA converter which never excerts a bad influence upon the quality of a reproduced sound by eliminating power consumption between a PWM(pulse width modulation) signal generating part and a low-pass filter. In the DA converter...
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JP2648573B2 |
PURPOSE: To correct an actual pulse width while data are being written, by using a concept of pre-correction. CONSTITUTION: A data source 150 creates a write signal, and supplies it to a variable edge control device to extend or shorten ...
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JP2646530B2 |
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JP2646756B2 |
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JPH09223958A |
To provide a binary/quaternary converting circuit device with which a wiring area is reduced and the number of output terminals is reduced into 1/2 by simplifying the circuit. The P gate input terminal of a transfer gate(TG) 11 is connec...
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JPH09214568A |
To reduce the noise of a driver. Timing control logic CONT1 and CONT2 start the supply of current to load by p-channel type MOS transistors MA3 and MB3 faster than the supply of current to a transformer 31 by p-channel type MOS transisto...
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JPH09214566A |
To precisely reproduce transmission data which a transmission station transmits on a reception side so as to prevent the deterioration of transmission efficiency even if noise gets into a communication line. When a reception station rece...
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