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JP2830352B2 |
In an apparatus for detecting input digital data, for example as derived by analog-to-digital conversion (6) of a reproduced binary signal in analog form, the input digital data is distributed into at least two channels, a processing cir...
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JP2827904B2 |
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JP2825042B2 |
PURPOSE:To stabilize an output bipolar signal by converting an input clock signal into a sine wave and using an inverter gate for the adjustment of the duty cycle. CONSTITUTION:An input clock signal 107 is given to an LC resonance circui...
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JP2826162B2 |
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JPH10308669A |
To reduce power consumption and increase operating speed by digitally converting an n-ary signal to a binary signal as all the bits or partial bits of the binary code. When the value of an analog signal Vin to be digitally converted to a...
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JP2824183B2 |
PURPOSE: To provide a system which is independent of a medium for coding and decoding binary data for serial transmission by performing conversion from an NRZ to an NRZI format, before performing supply to a transmission medium. CONSTITU...
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JP2824184B2 |
PURPOSE: To provide a serial data transmission system for guaranteeing that maximum accumulation DC shift on the average does not exceeds 10% over a transmission period. CONSTITUTION: A communication entity 410 is connected, so as to rec...
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JPH10511825A |
A NULL convention threshold gate (921) receives a plurality of inputs (X1, X2, ...Xn), each having an asserted state and a NULL state. The threshold gate switches its output (Z) to an asserted state when the number of asserted inputs exc...
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JP2821713B2 |
An encoder, decoder and encoder/decoder system utilizes quantization and adaptive bit allocation to encode and decode spectral information within frequency subbands. In accordance with spectral levels within a respective subband, bits ar...
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JP2818936B2 |
The invention provides a method of redundantly encoding 2 binary words into 2 encoded binary words, wherein m > n, well as circuits for the encoding and decoding of the encoded binary words. The m words exhibit x invariant bits between t...
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JP2816044B2 |
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JP2815858B2 |
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JPH10285040A |
To quickly reset an abnormal state to a normal state in a simple circuit constitution by outputting plural shifted signals which are obtained by shifting the CMI data at the fall of a synchronous clock, resetting the phase control of a d...
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JP2813866B2 |
To provide a phase-locked loop(PLL) including an ECL gate stage having controlled falling time. The fall-time of an ECL gate is exactly controlled while using a capacitor connected between a positive power source and the output of the EC...
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JP2811651B2 |
A method and apparatus for reducing storage requirements by lexicographically encoding/decoding state-dependent codes, and locally reordering coded subsequences to permit direct NRZ coding for particular applications in sequence detection.
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JP2809832B2 |
A code modulation system wherein an 8-bit input is converted to a 14-bit code by creating modulated data code tables and associating a given 8-bit input with a particular table based on the Digital Sum Variation value, the Non-Return to ...
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JP2810857B2 |
A system and method for encoding and decoding binary data for serial transmission over a physical medium provides a highly efficient and less complex coding scheme while guaranteeing clocking information and guaranteeing an NRZ(I)-dispar...
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JP2807293B2 |
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JP2809306B2 |
On the basis of n-bit words presented, the described channel encoder generates DC-free and run length limited m-bit (m n) code words having (1 + D)<-><1> or (1 + D<2>)<-><1> precoder properties. The m-bit code words are formed each time ...
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JP2806127B2 |
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JP2805096B2 |
This invention relates to a code modulating apparatus and a code demodulating apparatus for digital signals such as PCM audio signal, computer data, and so on. Input signal of M bits is divided (2) into a plurality of data bits and the c...
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JP2805604B2 |
An improved decoding apparatus for a Manchester code receives an asynchronous Manchester code, synchronizes to a received clock signal, and decodes an output NRZ code and an output synchronous clock signal. A first decoding unit samples ...
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JP2806872B2 |
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JPH10256921A |
To provide a digital data modulation/demodulation system which has a powerful error correction capability and has the processing simplified. At the time of modulation of digital data used for transmission or recording of N-bit (for examp...
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JP2803100B2 |
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JP2798718B2 |
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JPH10243031A |
To improve the reliability in the case of transfer of data by preventing mis-conversion in the case of binary conversion when a multi-value expression is realized by voltage differences. A conversion control section 6 continuously monito...
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JPH10233689A |
To provide the intermediate frequency modulator that eliminates the need of voltage adjustment with immunity to the effect of a temperature and a secular change. The intermediate frequency modulator 1 is provided with a coding means 11 t...
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JP2792042B2 |
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JP2791509B2 |
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JPH10224327A |
To provide a transmitter-receiver which adopts the start-stop system, is easily handled and in which coding/decoding is attained and a random bit error and a burst error are corrected without occurrence of consecutive bits. A coding sect...
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JP2786810B2 |
A recording medium having a SYNC (synchronous code) for synchronizing with data and a DCC (DC cancel code) for suppressing a DC component of a wave form of a signal recorded on the recording medium, the SYNC and the CDD being adjacently ...
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JPH10215184A |
To eliminate the need of an oscillator in a decoder by using one bit for specifying whole pulse width, calculating measuring time from whole pulse width and immediately measuring the signal level of a digital signal when measurement time...
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JPH10209856A |
To express a signal by dividing it into plural parts, and to allow the signal to have plural meanings by arranging plural levels necessary for a signal for signal detection with intervals in a height direction and a width direction, and ...
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JPH10208405A |
To provide a decoding system and a decoding method capable of simplifying a necessary logic circuit and reducing the number of memory cells required for decoding. In a system which decodes a coded word in EFM-plus and/or EFM format, an e...
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JPH10200588A |
To improve the identification ratio of data, while maintaining the sensitivity of a receiver and to improve the accuracy of a decoding signal by outputting 1st and 2nd comparison signals according to a comparison result of 1st and 2nd re...
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JP2777618B2 |
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JPH10190753A |
To avoid the risk of producing an artifact by providing a deviation with a positive value during a first period and a negative value during a second period and making the cumulative sum of the first period and the cumulative sum of the s...
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JP2773171B2 |
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JPH10173535A |
To provide a bipolar/unipolar conversion circuit which can extract a clock with no adjustment and also can reduce its overall scale. A clock extractor 2 of this conversion circuit consists of a digital PLL circuit including a phase compa...
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JPH10163878A |
To transfer parallel digital data in one signal line at one time. Digital signal decoder circuits 21 to 2n decode (n) sets of parallel digital data from a transmitting circuit 1. Voltage conversion circuits 31 to 3n convert decoded signa...
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JPH10163877A |
To set a fixed rate of the prescribed threshold against the level of a changed signal by controlling the relative value between the level of a detected received signal and the prescribed threshold set to a multi-valued comparator. A thre...
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JP2763709B2 |
PURPOSE: To provide a bit/dibit converting circuit of a simple constitution which is suited to a high speed operation. CONSTITUTION: A 2-divider 11 is provided to divide a bit rate clock into two clocks together with a synchronizing pres...
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JP2762528B2 |
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JPH10145233A |
To provide an interface circuit which processes either signal of an AMI(alternate mark inversion) code and a CMI(coded mark inversion) code and also makes it small. An interface circuit is provided with a receiving circuit 21 which recei...
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JPH10135838A |
To compose a CMI/NRZ conversion circuit of a digital circuit without using a phase locked loop circuit by converting a holding signal holding from the changing point of CMI(code mark inversion) code data at a middle point to the next mid...
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JPH10134522A |
To simplify a circuit configuration and reduce cost and at the same time compensate for a PPM coding signal for a DC drift and hence reduce noise, for example, from a reproduction head by decoding a pulse position modulation(PPM) coding ...
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JP2752874B2 |
A method for decoding F2F signals as well as a device for decoding F2F signals read from a magnetic data carrier is provided. The signal read from the card by a magnetic reading head 91 is amplified by an amplifier 912 with a very high g...
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JP2741112B2 |
A plurality of first codeword pairs (+3, -1) each including a 15-bit codeword of which CDS is equal to +3 and a 15-bit codeword of which CDS is equal to -1 and a plurality of second code pairs (+1, -3) each including a 15-bit codeword of...
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JPH1084323A |
To provide a receiver capable of realizing a higher bit transmission speed. This receiver includes an automatic gain control amplifier and an optical detection means that converts an optical signal into an electric signal from a data cha...
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