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JP2002031825A |
To provide an 'all optical' converter for converting an NRZ format input signal into an RZ format output signal.This is a converter of an NRZ signal with a bit duration T, which comprises an interferometer structure 10 having two pieces ...
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JP2002024979A |
To provide a multifunctional absolute converter having a high degree of freedom and capable of coping with the specifications of users.This multifunctional absolute converter has a sensor side input- output port 4 provided with a plurali...
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JP2002027464A |
To provide an encoder and a decoder which improve an error propagation suppression and ECC correction ability while avoiding increase in circuit size.The encoder includes a means for branching an RLL code into a restraining part correspo...
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JP3248382B2 |
PURPOSE: To provide an FM decoder which has a simplified circuit constitution and also can establish the synchronization in a short time. CONSTITUTION: An FM decoder includes a long cycle bit detection part 10 which detects a synchrnizin...
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JP2002501693A |
A system transmits digital information bits, which are encoded into a predefined number of signed symbols per frame from a transmitter (40) over a network (46) to a receiver, wherein the transmitted signed symbols have a desired spectral...
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JP3243140B2 |
PURPOSE: To provide a data conversion system which generates an RLL(run length limited) code that can perform the control to eliminate the DC component with no increase of the number of bits. CONSTITUTION: The conditions m
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JP3241980B2 |
To provide a communication system which transmits data at high speed with high reliability and is suitable particularly when applying to a vehicle. Plural node stations are connected on a bus line 1 to constitute a system and one of the ...
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JP3240341B2 |
PURPOSE: To reduce a DC component and a low frequency component after the coding and to prevent the occurrence of an error in a digital signal by monitoring the state of a DSV and selecting a code word. CONSTITUTION: Let an integral valu...
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JP3239663B2 |
PURPOSE: To provide a modulation method, modulator, and demodulator which reduce the peak value of DSV in comparison with that in a conventional device at the time of DSV control of the code where DSV control is not taken into considerat...
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JP3238053B2 |
To decode data by an error rate further more improved than a conventional error rate and to enlarge a margin. A clock extraction part 3 generates first clocks C1 synchronized with reproduced signals and the second clocks C2 of the double...
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JP2001339308A |
To provide a coder and decoder that can realize coding or decoding of a discrete signal at a high-speed with small power consumption.The coder/decoder is provided with a bit transition detection circuit 101, an analog conversion circuit ...
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JP2001525100A |
Data is detected from a disc in a disc drive and provided as a sampled read signal including data samples provided in a plurality of time intervals. A signal space detector is configured to detect the data, wherein the data is encoded ac...
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JP3235096B2 |
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JP3234525B2 |
To improve the system of m-n modulation so as not to largely change a DC level in m-n modulated and further NRZI modulated recording signals. Input data are stored for one block in a FIFO memory 2. For respective input (m)-bit data, by p...
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JP3232834B2 |
PURPOSE: To improve the data read rate by switching a pulse frequency received by a counter with an external control input so as to switch the discrimination coefficient of the demodulator. CONSTITUTION: A variable frequency divider 9 be...
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JP2001522186A |
A method for transmitting "biphase" encoded digital signals including the steps of setting an aperture corresponding to a data bit; dividing said aperture into a plurality of segments; setting a first segment, selected from said pluralit...
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JP3227901B2 |
PURPOSE: To perform high-density recording and make a maximum run (k) small by regarding bits at specific positions of a code whose maximum run (k) becomes ∞ and a code consisting of a maximum number of successive '0' s from the least ...
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JP2001306295A |
To provide an endian converter by which any trouble is not caused in the recognition of plural byte units without delaying an endian processing.This endian converter is provided with a first switcher (1a), which accepts input byte data(D...
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JP2001308710A |
To provide a modulation means capable of the pulse duration modula tion with high resolution while suppressing increase of the number of bits, and an LED display device provided with the modulation means.A video signal Sv transformed int...
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JP3222623B2 |
PURPOSE: To provide a data transmission/reception system where the number of both rise/fall edges and pulses is reduced to minimize the occurrent of noise. CONSTITUTION: A duty generating means 3 which generates the duty of a correspondi...
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JP3219773B2 |
An ATV system encodes variable length elementary streams of data into a multilevel symbol signal comprising a plurality of multiplexed fixed length data packets without sync information. The fixed length data packets are arranged in fiel...
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JP2001283533A |
To obtain an encoding device which can decide the value of a specific bit as determined by standards by a circuit with simple constitution. This device records data obtained by applying pulse-width modulation to write data, as recording ...
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JP2001518253A |
A method and apparatus for encoding data (15,) produces a code stream (153) of code words (190, 192, 194) where each code word includes two subsets of code bits. Each subset of code bits is constrained by a different maximum transition r...
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JP2001518254A |
An encoder (150) and a method of encoding successive data words (152) into successive code words (153, 180, 181, 182) having alternating code word lengths (260, 262). Each code word (153, 180, 181, 182) has a plurality of bit locations. ...
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JP3216145B2 |
PURPOSE: To transfer data at a higher speed by using two signal lines. CONSTITUTION: Four kinds of states are expressed by combinations of '1', '0' of two signal lines D1, D2, the state of the signal lines D1, D2 is changed without fail ...
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JP3217298B2 |
To provide nB2P encoder and decoder to simultaneously provide a line code function and a channel code function in a transmission line and a link. An nB2P encoder divides inputted parallel data into a fixed data unit, converts data that i...
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JP2001274688A |
To provide a decoder by which zero is inserted to the prescribed position of data for the purpose of discriminating data from non-data and the processing speed of zero deletion is improved in the case of decoding a binary signal to be tr...
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JP2001266499A |
To lower a decoding error rate by performing high-performance encoding and high-efficiency decoding.A magnetic recording and reproducing unit 50 is provided with a modulation-encoder 52 for applying prescribed modulation-encoding to inpu...
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JP3210983B2 |
PURPOSE: To discriminate a logic even under a very weak electric field strength by the discrimination method discriminating the logic based on a time width of a reception signal pulse. CONSTITUTION: A received signal is inputted to a cod...
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JP2001251191A |
To provide a circuit for decoding a Manchester-encoded transmission signal while suppressing the increase of errors.A multiplier 3 re-inverts bits (at every other bit) inverted at the time of Manchester encoding in transmission signals b...
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JP2001251370A |
To provide an inexpensive signal transmission system that can transmit a pulse width modulation signal with excellent reproducibility over a wide duty range while suppressing electromagnetic wave radiation, to provide a signal transmitte...
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JP2001251594A |
To provide a remote display device with which the screen of a computer terminal placed at a remote place can be read, without having to use exclusive softwares and which can secure high security.The RGB image signals shown on the display...
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JP3207997B2 |
PURPOSE: To efficiently attain data conversion, and to reduce a chip area by constituting a data converting device of a reduced lookup table and a logic circuit. CONSTITUTION: A data converting device is constituted of a reduced lookup t...
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JP3204217B2 |
To limit a repetition frequency of a 2Ts continuous pattern being the maximum repetition frequency in ordter to stably lock PLL in 1, 7 recording codes. Channel bits '00X', '010', '10X' are allotted to three patterns out of two data bits...
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JP2001512945A |
A detector is used in detecting data encoded in a read signal received from a storage channel. The detector includes a Viterbi detector having a time-invariant structure configured to detect the data encoded according to a code having ti...
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JP2001513305A |
An encoder for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, the bitstream of the source signal being divided into smaller n-bit source words (x1, x2) which are converted ...
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JP3201352B2 |
To obtain a synchronization circuit that prevents occurrence of unexpected synchronization outputs due to latch on the way of synchronization transition. An input signal Si is a signal with a 3-bit width that is incremented one by one, a...
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JP2001223591A |
To provide a digital compression system where a storage device or the like having an analog element stores an analog/digital synthesis signal pulse resulting from compressed digital code pulse by using a combination of an analog element ...
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JP2001223590A |
To provide a method used for an application of a power system storing phase information of a pulse width modulation(PWM) signal that is quantized.A digital audio amplifier (12) executes a method for noise shaping in one embodiment, a noi...
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JP2001511323A |
An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single te...
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JP2001511273A |
The present invention relates to a method of transmitting data in pulse intervals of a rotational speed signal, wherein the maximum number of the transmittable data is determined from the period of time which is required for transmitting...
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JP3190190B2 |
PURPOSE: To attain the run control of an I-NRZI conversion circuit. CONSTITUTION: Input data are applied to a delay element 13 through a selector 12. An output from the element 13 is applied to an I-NRZI conversion circuit 14 to execute ...
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JP3189648B2 |
To improve the data transfer capability by using a multi-value signal so as to transfer a bit string. Let a bit string in n-bit be [b(1),...b(n-1), b(n)], let an upper limit of a voltage range denoting a bit b(k) (n≥k≥1) be VDD(k), a...
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JP3170961B2 |
PURPOSE: To improve the response up to binary encoding by making it possible to deal with the counted values or the like of the upper and lower bits of a binary digital signal expressing a pulse phase difference. CONSTITUTION: A ring osc...
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JP2001144621A |
To provide a code conversion method and a code converter that can encode data so as to record the data with high density to a recording medium such as an optical disk. The code converter converts data by using a conversion table that is ...
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JP3167638B2 |
To improve the system of m-n modulation so that a DC level of a recording signal subject to m-n modulation and further NRZI modulation is not largely changed. To a head of input data, m-bit dummy data are multiplexed, an error check code...
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JP3166952B2 |
PURPOSE: To provide an inexpensive communication device by decoding a silent state and an in-reception-training state into '1', and then decoding pulse presence into '0' and pulse absence into '1' after start flag detection. CONSTITUTION...
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JP2001127640A |
To provide a recorder that can easily generate a synchronizing clock and does not cause increase in a data error rate after decoding. The recorder is provided with a 16/17 conversion circuit 25, a synchoronizing pattern addition circuit ...
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JP3163244B2 |
To provide the conversion circuit operated at a high processing speed. A frequency divider circuit 12 applies 1/8 frequency division to a 1GHz clock signal from a crystal oscillator 10 to generate a clock whose frequency is 125MHz, it is...
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JP2001505720A |
An interface circuit for use with process controllers permits analog signals to be input to a process controller through a binary interface of the process controller and permits analog signals to be output from the process controller thr...
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