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JP3063260B2 |
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JP3058997B2 |
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JP2000507381A |
Rate 24/25 modulation encoding methods and apparatus improve efficiency in a PRML magnetic recording channel. The rate 24/25 code word uses rate 8/9 RLL encoding of one byte of user data, combined with interleaved unencoded bytes to achi...
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JP3048960B2 |
To generate a clock signal synchronized with a binarized signal having the non-fixed length of one bit provided by FSK demodulation by providing a binary counting means having a specified function. A binary count means 62 counts decimal ...
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JP3048424B2 |
PURPOSE: To reduce the calorific value of a circuit, to attain a high integration, and to unnecessitate a radiating countermeasure by decoding an input signal whose transmission speed is high by logical elements whose operating speed is ...
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JP3044817B2 |
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JP3043067B2 |
PCT No. PCT/SE91/00501 Sec. 371 Date Jan. 13, 1993 Sec. 102(e) Date Jan. 13, 1993 PCT Filed Jul. 18, 1991 PCT Pub. No. WO92/01081 PCT Pub. Date Feb. 6, 1992.In a method for limiting the bandwidth of a selected binary signal (B), there is...
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JP2000138588A |
To provide a pulse width signal converting circuit which can surely uniformly convert pulse width signals. In converting PWM signals Di into parallel digital data, a pulse width signal converting circuit detects the rising edge of the si...
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JP3042201B2 |
PURPOSE: To make an output signal zero in the case a non signal is inputted without deteriorating the S/N characteristic of the noise shaper. CONSTITUTION: The noise shaper consisting of integration circuits S1 and S2 more than one stage...
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JP2000115261A |
To provide a data transmission system where power consumption required for transmission is reduced with respect to data at a high transition rate similarly to the case with data at a low transition rate.The data transmission system 200 h...
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JP3022816B2 |
To reduce the state change of a transmission signal and to easily transmit the data by sending the state transition time of the transmission signal to a transmission line in response to the transmission data value, converting the receive...
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JP3018973B2 |
To provide a circuit which can code-converts an RZ signal into an NRZ signal with sufficient phase redundancy. A clock signal ICLK which is phase-controlled in such a way that a frequency and the phase of a ruse edge become equal to thos...
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JP3018169B2 |
To reduce a wiring area by converting combinations with respect to changes in input signals received from a function block via lots of internal signal wires into a coded signal, outputting the converted signal to one signal transmission ...
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JP3015680B2 |
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JP3017379B2 |
The present invention provides an encoding and decoding apparatus used for the compression and expansion of data. A state machine is provided having a plurality of states. Each state has at least one transition pair. Each element of the ...
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JP2000068841A |
To shorten a period in which an output terminal becomes high impedance and to reduce the influence of noise received from the outside by providing an adjustment circuit for adjusting the duty factor of clock signals. In the case that thi...
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JP2000068835A |
To reduce a circuit scale and to lower its cost by making first and second digital signals share an analog circuit part provided in the poststage of a PWM conversion part. CD data inputted to a D/A conversion part 8 are finally converted...
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JP2000068834A |
To shorten conversion time by directly converting signals from one to the other or with each other between the digital data signals and the analog signals. In an upper region binary number, at least one of two adjacent digits is a combin...
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JP3012849B2 |
The audio transmission system samples and digitizes the audio input and separates it into subbands defined for psychoacoustic factors. The signals are pre-amplified (46) and then quantized (48) and combined for transmission. The pre-ampl...
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JP3013651B2 |
PURPOSE: To suppress a low frequency component by providing a recording density ratio DR in the digital modulator applying RLL coding to a digital signal so as to apply NRZI modulation to the coded signal. CONSTITUTION: A conversion info...
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JP2000059227A |
To precisely decode a code, which is obtained by decoding such as expressing digital data by a smaller number of bits, to original digital data without deteriorating precision. The continuing number of 0 is investigated from the lowest o...
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JP3011436B2 |
A digital signal modulator modulates an input digital data code to a channel code which has more bits than that of the input data code. The digital signal modulator comprises an NRZI transformer and a modulator. The NRZI transformer NRZI...
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JP3008400B2 |
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JP3009051B2 |
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JP3008659B2 |
PURPOSE: To stably execute an operation even when an AIS signal which is stipulated by means of CCITT is inputted. CONSTITUTION: A voltage control oscillator 1 executes oscillation in accordance with a control voltage Vc and outputs the ...
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JP2000040968A |
To make an encoder small-sized and to allow it to operate at a high speed. By the encoding method, (m)-bit data are converted into an (n)-bit code, which is a code generated according to a finite state transition chart representing the l...
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JP2000501265A |
The present invention defines a display driver for driving a flat panel display having rows and columns. The display driver has row and column drivers comprised of logic gates where each logic gate includes chalcogenide threshold switche...
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JP2000031946A |
To transmit a digital signal by way of a simple circuit means and a few signal lines. A transmission unit 1 accumulates digital transmission signals S11S1n so that they are a multi-level signal (m) with plurality of logic signal levels. ...
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JP2000022542A |
To provide a charging/discharging circuit of a small scale by using a differential circuit which performs charging/discharging operations by means of charging/discharging current received from a current source and based on a control sign...
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JP2999175B2 |
To provide the data encoding method of an optical disk capable of realizing a high speed and a high density. In the data encoding method of an optical disk 10 which has the track 11 of a dual spiral structure having an adjecent first spi...
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JP3000334B2 |
A digital decoder for a biphase-mark encoded serial digital signal detects edges in the encoded serial digital signal by sampling with a sample clock to produce a blivet signal. The blivet signal is filtered by a one-bit digital lowpass ...
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JP2994265B2 |
To reduce a memory capacity required for coding/decoding by decoding a transmission code in parallel n-bit into r-bit (m≤r≤n) under the condition of a minimum run length and decoding the code into m-bit code data. An S/P converter 10...
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JP2993817B2 |
PURPOSE: To simplify the circuit configuration and to make the manufacturing cost low by generating and transmitting a binary digital signal having at least a leading part rising steeply at a 1st signal level and a trailing signal part d...
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JPH11330978A |
To simultaneously perform addition processings for each digit and to shorten operation time by handling a head binary number, i.e., a combination of signals 'o' showing zeros as a scale of notation for at least one of two digits which ar...
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JPH11317774A |
To obtain a fast data link executing serial data transmission by providing a pulse amplitude modulating encoder, a transmitter, a receiver and a pulse amplitude demodulating decoder for pulse amplitude modulation encoded data which shoul...
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JP2972657B2 |
A system for controlling the frequency of a bit synchronizing clock signal used for reproducing an EFM signal, comprises an EFM signal frame period detecting circuit for frequency-dividing an EFM signal by 117 to output a +E,fra 1/117+EE...
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JPH11308281A |
To provide a digital signal transmitter capable of reducing power consumption in sending a digital signal. An encoder 39 generates a digital signal T1 whose lever is switched between 1st and 2nd levels in a timing when a toggle produced ...
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JP2969375B2 |
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JPH11288563A |
To provide a system encoding data field on a disk with writing gate data. A system has an encoder and a controller for receiving data guiding writing gate data to the encoder with a form of 0 bit and 1 bit. The encoder responds to writin...
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JP2964899B2 |
PURPOSE: To provide encoding/decoding frequency synchronizing method by which the frequencies of an encoding device-side and a decoding device-side can be synchronized with the constitution of a small scale. CONSTITUTION: A clock generat...
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JP2965448B2 |
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JPH11284671A |
To enable a highly reliable serial transmission at a low cost with a small circuit scale by preventing multistage propagation of a pathological signal (pattern data with maximum component, etc.), and minimizing a cumulative increase of j...
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JP2957665B2 |
A HDB3 code violation detector includes a converting part (1) for receiving positive polarity data and negative polarity data from a PCM line and for converting a HDB3 code received via the PCM line into an NRZ signal, a first judging pa...
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JPH11511283A |
PCT No. PCT/US96/12680 Sec. 371 Date Apr. 21, 1997 Sec. 102(e) Date Apr. 21, 1997 PCT Filed Aug. 2, 1996 PCT Pub. No. WO97/06624 PCT Pub. Date Feb. 20, 1997An encoder for matched spectral null binary codes is described, particularly for ...
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JPH11266158A |
To reduce the maximum value and the average of the number of bits which change at the sometime, in the transmission of a logical signal. This device is equipped with a logical circuit 100, which converts a logical signal of n bits into m...
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JP2951992B2 |
This method is characterized in that the data is encoded in the form of blocks of four bits in five-bit words, three bits (7) of each block being encoded according to the NRZ encoding method and one bit (8), according to the Manchester e...
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JPH11252187A |
To provide an improved circuit for decoding an input digital signal or a stream by generating a signal which is phase-locked by a digital input signal encoded in accordance with two-phase modulation from a master clock signal. In the cas...
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JP2947074B2 |
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JP2941713B2 |
Data detection method and apparatus in a data storage device are provided. The data detection apparatus includes: a Random Access Memory (RAM) updating device for obtaining the average characteristic of the equalization signal zk from th...
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JP2940261B2 |
PURPOSE: To provide the serial communication method for the vehicle use arithmetic operation processing unit in which data communication is implemented at a high speed with high accuracy and simple configuration. CONSTITUTION: In the ser...
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