| Document |
Document Title |
|
JP3454529B2 |
PURPOSE: To simplify and stabilize the control system of a magnetic bearing device and reduce the cost thereof by providing a pulse-width modulation type power amplifier, in which output pulse width has the square root operation characte...
|
|
JP3455008B2 |
To realize an optical signal demodulator in which malfunction is hardly caused and the pulse width of a received code signal is accurately demodulated. A photodiode 1 receives an optical code signal modulated by a pulse with a prescribed...
|
|
JP2003264598A |
To realize the shortening of a full transmission time and the power saving of a data transmitter by using variable length codes.In the encoding technique using variable length codes in wireless communication, a transmission time for the ...
|
|
JP3442279B2 |
To provide a control device, for a material testing machine, by which an item condition used to specify a test condition can be input and controlled by using a screen, interactively, simply and efficiently. A setting-content screen 1 by ...
|
|
JP2003526222A |
(57) [Summary] It is a vehicle information system including a tag system (120B) installed in the vehicle (100). This tag system (120B) transmits vehicle-related data obtained from the vehicle (100) to the interrogator (300B). This vehicl...
|
|
JP3436400B2 |
PURPOSE: To convert one ternary input signal to two binary signals with a 2nd node as an input terminal while connecting the 1st and 3rd nodes of three nodes among four resistors through 1st and 2nd threshold value deciders to a logic ci...
|
|
JP3429821B2 |
PURPOSE: To provide a quantum device which can execute a complicated logical function with a single device, operates at a temperature higher than a room temperature, and can be programmed electrically to perform a plurality of kinds of l...
|
|
JP2003209496A |
To minimize inter-symbol interference caused by the dispersion of energy in a received non-return to zero (NRZ) data channel and further to modify a bit decision threshold while taking into account the dispersed energy in the neighboring...
|
|
JP2003208764A |
To provide a modulating device the circuitry of which is simplified that can be easily applicable to other systems.A pattern conversion section 32 converts data whose basic data length is 2-bits fed to a DSV (Digital Sum Value) control b...
|
|
JP3428039B2 |
PURPOSE: To quickly recover step out by providing a detecting circuit which extracts an edge part of a recorded signal detected with binary and makes it a pulse train, a latch circuit which keeps numbers of channel lock of which inversio...
|
|
JP3428191B2 |
PURPOSE: To attain accurate pulse width communication in the case of communication between different microcomputers by correcting pulse width of a transmission pulse signal to decode transmission data when a received pulse signal is a tr...
|
|
JP3426191B2 |
To obtain a method and a device capable of simply substituting a circuit realized by miniaturized digital logic for a PLL circuit. In order to measure a pulse interval for encoding data information by utilizing a high frequency signal al...
|
|
JP3425767B2 |
A clock signal is generated, from a biphase modulated, digital signal, by means of two samples (TF, TB) per symbol interval, T. This pair of samples are spaced at about T / 4. The clock is generated by, firstly, shifting the pair of samp...
|
|
JP3423693B2 |
A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential...
|
|
JP3423013B2 |
PURPOSE: To reduce the possibility of synchronization, having an error by determining the temporary position of inserted synchronizing sequence in comparison with the prescribed bit sequence of synchronizing sequence. CONSTITUTION: A mag...
|
|
JP3424600B2 |
To extract a reception clock with an optimum phase by surely detecting a preamble independently of an operating frequency without the use of a fixed delay circuit. The receiver consists of a preamble detection circuit 101 that detects a ...
|
|
JP3425152B2 |
Encoding arrangement for encoding a sequence of (n-1)bit information words into a sequence of n-bit channel words, and a decoding arrangement for decoding a sequence of n-bit channel words into a sequence of (n-1)-bit information words. ...
|
|
JP3419520B2 |
PURPOSE: To provide a method and device for reducing or eliminating the possibility of an undetectable error generated due to a noise contaminating the data of continuous blocks propagating in parallel through channels which simultaneous...
|
|
JP3416115B2 |
A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cy...
|
|
JP3413747B2 |
To efficiency transmit audio signals by infrared rays while suppressing the complication of data processings at the time of modulation and at the time of demodulation to minimum. The audio signals reproduced in a digital audio equipment ...
|
|
JP3415121B2 |
Encoding and decoding systems and methods for digital data in 24 bit sequences. An encoder generates state variables as a function of four or fewer bits of the 24 bit sequence, and encodes the sequence into 11 and 14 bit codewords. After...
|
|
JP2003162870A |
To provide a phase comparator circuit and a PLL circuit incorporating it, which can correct LSB errors in code conversion of the wave data read from a magnetic recording medium, avoid increase in circuit scale and in delay, while realizi...
|
|
JP3409246B2 |
To increase the information quantity of data without increasing the number of data. At the time of reading a ternary data signal and converting data, the voltage level of the ternary data signal, which is read at every reading of the ter...
|
|
JP3408256B2 |
A a series of m-bit information words is converted to a modulated signal. For each information word from the series, an n-bit code word is delivered. The delivered code words are converted to the modulated signal. The code words are dist...
|
|
JP3406440B2 |
To perform demodulation without being affected by frequency characteristics by expressing the respective states of bit data at the time interval of rise and the time interval of fall of a converted pulse unit signal. A serial-parallel co...
|
|
JP3405916B2 |
To perform conversion from a Manchester code to an NRZ code without using the identifier of double speed. The phases of the Manchester code of input and an encoding clock are compared in a phase comparator 7, phase comparator output is s...
|
|
JP3403366B2 |
To provide transmission information of excellent quality with less noise from the low frequency band components of pulse signals on a reception side by reducing low frequency band conversion noise in the transmitted pulse signals in the ...
|
|
JP3399950B2 |
The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal different...
|
|
JP2003122433A |
To achieve good transmission even if the length of wiring interconnecting an encoder for detecting the position information of a rotating machine or the like and a controller controlling the position and speed of the rotating machine usi...
|
|
JP2003514341A |
A device and associated method for processing a digital information signal from a channel signal. The digital information signal is runlength limited with one or more constraints. The device comprises receiving means for receiving the ch...
|
|
JP2003110376A |
To correct distortions generated in an amplifier.A signal amplifier is provided with a delta-sigma modulating means, pulse width modulating (PWM) means, amplifying means, rise detection means, fall detection means, calculating means and ...
|
|
JP3394127B2 |
To reproduce information data with high accuracy. Digital data are contained in a sector consisting of plural synchronization frames and sent sequentially. The synchronization frame consists of a synchronizing signal and a run length lim...
|
|
JP2003101412A |
To prevent the output of an erroneous analog output signal when supplying input data having an error to a digital/analog (D/A) converter having a serial interface.A D/A converter 147 has the serial interface. In data D1-Dn as control sig...
|
|
JP3390198B2 |
PURPOSE: To well transmit data by adjusting a sampling point according to a timing error signal to sample a received signal at a correct point of time. CONSTITUTION: Inputs a2i-1, a2i of encoders 8, 10 of a transmitter 2 are transmitted ...
|
|
JP2003051859A |
To realize a data transmission system that can replace a binary signal replaced with a ternary signal and transmit it and attains tight impedance matching with a transmission line on a single power supply voltage. The transmission system...
|
|
JP2003504778A |
A data storage channel encoder includes a data word input, a code word output and an encoder. The encoder is coupled between the data word input and the code word output and is adapted to encode successive data words received on the data...
|
|
JP2003032120A |
To provide a code generation and arrangement method providing a high efficiency from the standpoint of recording density by using a short codeword bit as the length of a main conversion codeword and having higher DC suppression capabilit...
|
|
JP3371911B2 |
A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit yk=0 when the corresponding bit xk=0; bits yk alternatively a...
|
|
JP3368861B2 |
To use data with parallel data buses of defined width together with a circuit which transmits and receives by providing plural inputs which receive a 1st set of parallel data and ≥1 outputs which transmit a 2nd set of parallel data sig...
|
|
JP2003018012A |
To provide a method for generating a digital modulation signal for DSV(digital sum value) control with high performance producing no low frequency component in the case of generating the digital modulation signal by run length coding and...
|
|
JP2003018009A |
To provide a digital/analog converter that can reduce the effects of clock jitters and utilize the PWM or PDM(pulse density modulation).The digital/analog converter makes either or both of leading and trailing PDM pulses in a stepwise fo...
|
|
JP3363432B2 |
To provide a merit for obtaining an MTR code, to simplify an encoder and to efficiently realize a high code rate code by dividing an input data word and applying encoding and violation correction to satisfy a specified restriction. A 16-...
|
|
JP2003500884A |
The invention provides for an apparatus for decoding a serial datastream of channel words into a datastream of information words. The apparatus comprises an input terminal (10) for receiving the serial data stream of channel words, a ser...
|
|
JP3355666B2 |
A modulator for suppressing a low-frequency component of a recording waveform while limiting maximum and minimum recording wavelengths, includes a margin bit generating circuit (40A) for generating a most suitable margin bit pattern base...
|
|
JP3354829B2 |
A differentiating circuit and a clock generating circuit that do not include unwanted frequency components in a differentiated signal. An inverted signal of an NRZ (Non Return Zero) data signal is delayed by a fixed time in a delay circu...
|
|
JP2002335160A |
To generate DC-free channel code words composed of given number of symbols, based on non-DC-free code words, composed of fewer number of symbols, thereby reducing the mounting complexity for generating the code words.Code words are selec...
|
|
JP3347667B2 |
In a Manchester encoded data decoder a clock component is extracted from input data inputted at a prescribed rate, the extracted clock component is taken as input and transition points are extracted from the signal waveform of the filter...
|
|
JP3343148B2 |
PURPOSE: To lower the frequency band required for the exclusive OR circuit in the phase detecting circuit and to place the phase detecting circuit in normal operation even for a data signal which has large waveform deterioration. CONSTIT...
|
|
JP3344530B2 |
|
|
JP2002323944A |
To realize a multilevel voltage signal bus interface circuit, with which bus width (number of signal lines) is reduced by converting n-bit parallel data to the multilevel voltage signals of 2-squared stages and supplying them to a bus, w...
|
