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WO/2023/287407A1 |
In one example in accordance with the present disclosure, an electronic device is described. An example electronic device includes a volatile memory device and a non-volatile memory device. The example electronic device also includes a c...
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WO/2023/284091A1 |
Disclosed in the present disclosure are a detection method for a memory and a detection apparatus for a memory. The detection method comprises: a memory comprising a first storage unit, a second storage unit, a bit line, a complementary ...
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WO/2023/287061A1 |
The present invention relates to a NAS memory cell having a NAND flash memory and an SRAM fused therewith, and a NAS memory array using same. An NST unit is connected to a first data node of an SRAM cell together with a NAND flash string...
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WO/2022/234128A9 |
The invention relates to an apparatus according to one embodiment. The apparatus comprises a control unit (110) and a memory unit (120). The memory unit (120) comprises a memory which has a plurality of memristors. The control unit (110)...
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WO/2023/287955A1 |
An integrated circuit device includes an anti-fuse device. The anti-fuse device includes a cup-shaped bottom anti-fuse electrode, a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode,...
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WO/2023/287877A1 |
Methods, systems, and storage media for recording moments as they are occurring and utilizing a virtual assistant to re-play those moments as a fully or partially immersive experience are disclosed. Exemplary implementations may: record ...
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WO/2023/288062A1 |
A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unus...
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WO/2023/286547A1 |
A memory device (10) comprises: a memory cell (14) including a first region (R1) and a second region (R2) capable of being written to only once; and a control unit (2). First region information relating to a region in which data to be wr...
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WO/2023/284094A1 |
Provided in the embodiments of the present application is a layout structure of an anti-fuse array. The layout structure of an anti-fuse array at least comprises an array circuit region and a functional circuit region, wherein the array ...
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WO/2023/284090A1 |
Disclosed in the present invention are an all-optical Boolean logic device based on a phase-change material and a binary logic implementation method thereof. The all-optical Boolean logic device comprises three Y-branch waveguide structu...
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WO/2023/284395A1 |
A voltage conversion circuit (100) and a memory. The voltage conversion circuit (100) comprises: a driver circuit (1), to which power is supplied by a first voltage (Vcc), wherein an output terminal outputs a first signal (S1), and the v...
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WO/2023/286626A1 |
Provided is a fluorine-containing ether compound that can form a lubricating layer with which it is possible to raise the chemical resistance of magnetic recording media even when the layer is thin and that can be used suitably as a mate...
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WO/2023/287474A1 |
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertic...
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WO/2023/282057A1 |
The present invention provides a storage device that writes, with pulsed light for communication, data transmitted by the pulsed light for communication.　Through irradiation of bright unit pulses, the temperature is increased, the magn...
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WO/2023/280964A1 |
The invention relates to an optical writing method in a semiconductor material (10), the method comprising laser writing in volume of the semiconductor material. The method comprises, prior to laser writing, irradiating the semiconductor...
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WO/2023/279140A1 |
A video display system (10) for displaying activity clips (3) in a set of activity clips, the video display system (10) comprising a processing sub-system (14) and a visual display sub-system (18). The visual display sub-system (18) is c...
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WO/2023/283047A1 |
The present invention includes apparatus and a method for reading one or more data states from an integrated circuity memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having ...
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WO/2023/282961A1 |
In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell...
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WO/2023/281250A1 |
A method of compositing a video stream comprising the steps of: obtaining first and second video streams, wherein there is overlap between the background of the first and second video streams; identifying a common feature in the backgrou...
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WO/2023/282923A1 |
Numerous embodiments are disclosed for programmable output blocks for use with a VMM array within an artificial neural network. In one embodiment, the gain of an output block can be configured by a configuration signal. In another embodi...
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WO/2023/279607A1 |
The present disclosure relates to an input sampling system and method, a storage medium, and a computer device. The system comprises: a signal processing module, configured to receive an initial chip select signal and a command/address s...
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WO/2023/279495A1 |
Provided in the present disclosure are a semiconductor device testing method and a semiconductor device testing apparatus. The testing method comprises: forming a plurality of test values according to a first retention time range and a f...
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WO/2023/281107A1 |
The disclosed technology provides solutions for enhancing a user's experience of music video playback. Beat temporal locations are identified in the soundtrack of a multimedia content item, and surround the beat temporal locations, the p...
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WO/2023/279542A1 |
Provided in the embodiments of the present disclosure is an anti-fuse storage circuit, comprising: a storage array, which comprises a plurality of anti-fuse storage units; bit lines, which are connected to the anti-fuse storage units tha...
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WO/2023/281728A1 |
A dynamic flash memory is formed by stacking, on a P-layer substrate 20, a first dynamic flash memory cell and a second dynamic flash memory cell, wherein the first dynamic flash memory cell is formed as a first Si pillar 22a comprising ...
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WO/2023/279345A1 |
Embodiments of the present application provide a magnetic random access memory (MRAM) and data writing and reading methods therefor, and an electronic device, which relate to the technical field of storage, and which can solve the proble...
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WO/2023/279480A1 |
Disclosed in embodiments of the present application are an input sampling method and circuit, a memory, and an electronic device. The method comprises: acquiring a first pulse signal and a second pulse signal, respectively; and then broa...
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WO/2023/279478A1 |
Embodiments of the present application provide a compiling method, a compiling circuit, a mode register, and a memory. The compiling method comprises: receiving a signal to be compiled and an operating frequency signal; compiling the sig...
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WO/2023/279948A1 |
A data storage circuit and a control method therefor, and a storage apparatus. The data storage circuit (100) comprises a first storage array (10) and a sense amplifier array (20), wherein the first storage array (10) is located at one s...
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WO/2023/282891A1 |
A print cartridge circuitry component comprising an integrated circuit for association with a plurality of fluid actuation devices and comprising input signal contacts to receive input signals from a host printer. The integrated circuit ...
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WO/2023/281730A1 |
In this invention, a strip-shaped P-layer 2 is provided on an insulating substrate 1. Further, on both sides of the P-layer 2 in a first direction parallel to the insulating substrate, an N+ layer 3a connected to a first source line SL1,...
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WO/2023/279479A1 |
Provided in embodiments of the present application are a compilation method, a compiling circuit, a mode register, and a memory. The compilation method comprises: receiving a signal to be compiled and a resistance matching signal; compil...
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WO/2023/279552A1 |
Embodiments of the present invention disclose a memory, comprising: a repository, the repository comprising multiple memory blocks, the memory blocks each comprising multiple word lines, multiple bit lines, and multiple memory cells arra...
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WO/2023/279511A1 |
An enable control circuit (40) and a semiconductor memory (90). The enable control circuit (40) comprises: a counting module (41) used for counting a current clock cycle, and determining a clock cycle count value; a selection module (42)...
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WO/2023/281613A1 |
The following operations are performed: a page write operation in which voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each memory cell included in ...
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WO/2023/282941A1 |
An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the sta...
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WO/2023/283073A1 |
A processor unit includes a memory and an ALU coupled with the memory. The processor unit also comprises a test controller, a test control register, and a signature register. The test controller manages a series of steps to test the proc...
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WO/2023/281610A1 |
A glass plate according to an embodiment of the present invention is a rectangular plate that has a plate thickness of less than 0.68 mm. In the glass plate, a 100 mm side square region for measurement that has been cut out from a centra...
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WO/2023/283518A1 |
Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation as...
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WO/2023/279352A1 |
A magnetic random access memory (MRAM) (200) and a data writing and data reading method therefor, and an electronic device, relating to the technical field of storage, and capable of solving the problem of difficulty in wiring caused by ...
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WO/2023/272804A1 |
A signal generation circuit and method, and a semiconductor memory. The signal generation circuit comprises: a clock module (310), which is used for receiving a flag signal and generating a clock signal; a control module (320), which is ...
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WO/2023/278946A1 |
Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A method may include writing memory cells to an intermediate state based on receiving a write command. Writing the intermediate state...
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WO/2023/276224A1 |
The magnetic resistor element according to the present embodiment comprises: a first magnetic layer (11) which is stacked on a base layer (10); a second magnetic layer (13); and a first non-magnetic layer (12) which is positioned between...
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WO/2023/274928A1 |
An asynchronous circuit portion (2) for sampling an input signal (14) is provided. The asynchronous circuit portion comprises a sampling circuit portion (4) arranged to receive the input signal and to generate first and second sample sig...
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WO/2023/275514A1 |
There is provided a data processing apparatus and method. The data processing apparatus comprises a plurality of processing elements connected via a network arranged on a single chip to form a spatial architecture. Each processing elemen...
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WO/2023/272917A1 |
A sparse matrix storage and computation system and method, which belong to the field of microelectronic devices. The system comprises: a first storage array, which is used for storing a coordinate index table of non-zero elements of a sp...
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WO/2023/278073A1 |
Methods and systems include memory devices (100) with a memory array (112) comprising a plurality of memory cells (102). The memory devices (100) include a control circuit (122) operatively coupled to the memory array (112) and configure...
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WO/2023/272788A1 |
Embodiments of the present application disclose a signal generation circuit and method, and a semiconductor memory. The signal generation circuit comprises: a clock module, configured to generate a clock signal on the basis of a flag sig...
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WO/2023/272470A1 |
The present disclosure provides buffer circuits of 3D NAND memory device. The buffer circuit comprises a first bit line segment sensing branch (630) connected to a first bit line segment and including a low-voltage latch (620), and a sec...
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WO/2023/278380A1 |
Techniques for generating action recommendations for a data tape system based on a media drive calibration are disclosed. A system receives a request to perform an operation including an exchange between a data tape and a media drive. If...
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