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WO/2023/275509A1 |
A photonic content addressable memory (CAM) (100) is provided. The photonic CAM (100) comprises: N search lines (101) and a plurality of match lines (102), each match line comprising N photonic CAM cells (110). Each search line (101) is ...
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WO/2023/276608A1 |
This alkali-free glass panel is characterized by having a glass composition containing, in mol%, 64-72% of SiO2, 11-15% of Al2O3, 0-4% of B2O3, 0-0.5% of Li2O+Na2O+K2O, 5-12% of MgO, 7-12% of CaO, 0-1% of SrO, 0-1% of BaO, and 15-19% of ...
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WO/2023/276954A1 |
Provided is a fluorine-containing ether compound that has excellent abrasion resistance even when the thickness thereof is low, and that can form a lubrication layer in which a reduction in film thickness caused by spin-off is unlikely t...
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WO/2023/272550A1 |
In certain aspects, a memory device includes a bit line, a plurality of memory cells coupled with the bit line, and N selectors, where N is a positive integer greater than 1, and N word lines. Each one of the plurality of memory cells in...
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WO/2023/278049A1 |
A memory system includes a column circuit to generate a logic state of data stored in one of the memory bit cell circuits in a column in a read operation. The column circuit includes a read control circuit to cause a float control circui...
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WO/2023/276733A1 |
A first fuse unit 110 and a second fuse unit 120 have the same configuration. A rectifier element 112 is connected in parallel to the fuse element. The drain of a first transistor M11 is connected to a second terminal of the fuse element...
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WO/2023/273185A1 |
The present invention provides a preparation method for an optical fiber data storage device, comprising the following steps: S1, processing data information to be stored and converting same into data of a unified number system; then acc...
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WO/2023/279004A1 |
Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes first computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM ...
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WO/2023/278947A1 |
Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory...
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WO/2023/278185A1 |
A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends acros...
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WO/2023/277240A1 |
A resistive random access memory having a BICS structure, and an operation method therefor are disclosed. A resistive random access memory according to one embodiment may comprise: a plurality of horizontal electrode layers which extend ...
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WO/2023/278173A1 |
A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series...
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WO/2023/278008A1 |
Various apparatuses, systems, methods, and media are disclosed to provide a heat-assisted magnetic recording (HAMR) medium that has a magnesium (Mg) trapping layer that is configured to mitigate Mg migration in the HAMR medium so as to p...
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WO/2023/272614A1 |
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structu...
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WO/2023/272471A1 |
Page buffer circuits of 3D NAND devices, and the page buffer circuit comprises a first bit line segment sensing branch (630) connected to a first bit line segment of a bit line, and a second bit line segment sensing branch (640) connecte...
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WO/2023/276292A1 |
An information processing device according to the present invention comprises: an information acquisition unit that acquires information regarding the length of a moving image template and information regarding the length of a material m...
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WO/2023/272548A1 |
A method of data protection for a three-dimensional NAND memory, the method includes programming a memory cell of the 3D NAND memory according to programming data; and backing up a portion of the programming data associated with the memo...
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WO/2023/278204A2 |
DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the reten...
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WO/2023/277965A1 |
Techniques are disclosed for allowing remote participation in collaborative video review based on joint state data, for a video collaboration session, maintained by a video collaboration service. A user at a participant client device may...
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WO/2023/278948A1 |
Methods, systems, and devices for sensing techniques for differential memory cells are described. A method may include selecting a pair of memory cells that comprise a first memory cell coupled with a first digit line and a second memory...
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WO/2023/278189A1 |
Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal...
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WO/2023/272627A1 |
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure a...
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WO/2023/272896A1 |
A signal generation circuit and method, and a semiconductor memory. The signal generation circuit comprises: a clock module (310), configured to receive an external clock signal and generate an internal clock signal; a control module (32...
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WO/2023/273554A1 |
A readout circuit structure, comprising: a first sensing amplification circuit (113) and a second sensing amplification circuit (123), which are adjacently arranged in an extension direction of a bit line, wherein the first sensing ampli...
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WO/2023/272585A1 |
Embodiments of the present application provide a method and apparatus for testing a memory, which relate to the technical field of chips, and are used to solve the problems of high overhead, high delay and complex circuit design when per...
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WO/2023/277966A1 |
Techniques are disclosed for avoiding conflicting user actions while the users synchronously participate in collaborative video review based on joint state data for a video collaboration session. User actions may conflict, e.g., when a u...
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WO/2022/269660A1 |
This drive circuit comprises: a load resistor; a resistance changing element having at least a first terminal and a second terminal, and capable of changing a resistance value; and a constant current source that decides the magnitude of ...
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WO/2022/271484A1 |
A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a wri...
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WO/2022/266985A1 |
In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. ...
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WO/2022/272029A1 |
An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected t...
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WO/2022/268604A1 |
The present invention pertains to a method for switching magnetic moments in a magnetic material, comprising the steps of: a) heating a system comprising - a layer of the magnetic material and - a layer of a metal which is in contact wit...
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WO/2022/269493A1 |
A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line ...
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WO/2022/272184A1 |
An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line wh...
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WO/2022/271653A1 |
Embodiments of the present invention are directed to systems, devices, lockable enclosures, and methods for data centers. In one example, a lockable enclosure for a data drive is provided. The lockable enclosure includes a housing config...
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WO/2022/270323A1 |
A memory device comprises: a word-line selection unit (X decoder) configured to select a word line; a memory cell including cells that are connected to the word line and each bit line and are disposed in a matrix form; a bit detection un...
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WO/2022/268726A1 |
The invention relates to a method for detecting at least one error caused by a photoelectric or radiative phenomenon in a non-volatile semiconductor memory, the memory comprising a plurality of memory cells (CM) with MOS transistors, pos...
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WO/2022/272183A1 |
An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored d...
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WO/2022/268133A1 |
The present disclosure provides a template recommendation method and apparatus, a device, and a storage medium. The method comprises: first, obtaining a feature of a multimedia material to be processed; then, determining a similarity bet...
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WO/2022/270890A2 |
The present invention relates to a technology for independently connecting and forming, through interconnection layers, a plurality of neuromorphic devices that are 3-dimensionally stacked and formed on a complementary metal-oxide semico...
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WO/2022/271206A1 |
Magnetic recording media including a soft magnetic underlayer (SUL) formed over a plasma-polished substate or pre-seed layer. In some examples, the substrate or pre-seed layer is plasma-polished using an inert gas such as krypton so that...
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WO/2022/271695A1 |
A four-channel memory module includes four independent twenty (20) data bit memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the me...
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WO/2022/269735A1 |
This memory device is provided with a page made from multiple memory cells arranged in columns on a substrate, and carries out: a page write operation for holding, inside a channel semiconductor layer, a hole group formed by an impact-io...
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WO/2022/271208A1 |
A magnetic recording medium includes a substrate, a soft magnetic underlayer on the substrate, and a dual seed layer. The dual seed layer includes a first seed layer comprising NiFe at a first concentration, and a second seed layer compr...
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WO/2022/268416A1 |
According to one embodiment, a method, computer system, and computer program product for increasing linearity of a weight update of a phase change memory (PCM) cell is provided. The present invention may include applying a RESET pulse to...
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WO/2022/269492A1 |
A low-power static random access memory (SRAM) is set forth which includes a cache memory function without requiring a special bit cell, and which realizes robust read and write operation without any write assist circuit at 16nm or below...
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WO/2022/271207A1 |
Magnetic recording media including a soft magnetic underlayer (SUL) formed over an oxidized pre-seed layer. In some examples, the pre-seed layer is oxidized to reduce an amount of intermixing between the pre-seed layer and the SUL. The r...
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WO/2022/269740A1 |
This memory device comprises a page constituted by a plurality of memory cells arranged in columns on a substrate, said memory device performing: a page write operation for controlling voltages to be applied to a first gate conductor lay...
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WO/2022/265693A1 |
Embodiments of the present disclosure generally relate to a vertical cavity surface emitting laser, a head gimbal assembly for mounting a vertical cavity surface emitting laser, and devices incorporating such articles. In an embodiment, ...
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WO/2022/266009A1 |
An application specific integrated circuit (ASIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The ASIC can include a supply and reference voltage generation circuit, a digital core, a clock genera...
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WO/2022/264956A1 |
The present invention provides a magnetic recording medium that has a non-magnetic support and a first magnetic layer that includes a ferromagnetic powder and a binding agent, the magnetic recording medium also having a second magnetic l...
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