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WO/2022/262766A1 |
Disclosed is an automatic clipping method. The method comprises: S1: smoothing a scoring curve of a video to be clipped; S2: calculating maximum points and minimum points in the smoothed scoring curve; S3: obtaining at least one prelimin...
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WO/2022/265845A1 |
Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the ...
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WO/2022/261890A1 |
A read operation circuit, comprising a voltage follower and a sense amplifier. The voltage follower and the sense amplifier are respectively coupled to a cross-point memory array; the cross-point memory array comprises multiple columns o...
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WO/2022/264476A1 |
This semiconductor storage device has a first memory cell group to an eighth memory cell group that are arranged along a first direction; a first word line extending in the first direction; and a first sense amplifier group to an eighth ...
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WO/2022/262668A1 |
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input fr...
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WO/2022/265688A1 |
Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply analog weights to input data using multiply- accumulate operations to g...
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WO/2022/261920A1 |
Disclosed in embodiments of the present application are a data processing method and apparatus, a display terminal, and a medium. The method comprises: acquiring user input information, the user input information being used for indicatin...
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WO/2022/266583A1 |
Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a ...
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WO/2022/265689A1 |
Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply a plurality of analog weights to data using multiplyaccumulate operatio...
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WO/2022/266596A1 |
A time-lapse imaging system is provided that may include an image capture device, an intervalometer coupled to the image capture device for controlling an interval at which the image capture device captures an image of one or more object...
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WO/2022/264903A1 |
A control circuit 13 is a circuit for reading data from a memory array 11 having bit lines BL electrically connecting memory cells MC, said circuit comprising: an amplification unit 33 which has read lines RL connected to the bit lines B...
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WO/2022/262017A1 |
Disclosed are a memristor-based complete nonvolatile Boolean logic circuit and an operation method. The memristor-based complete nonvolatile Boolean logic circuit is used for performing logic operation on an inputted logic value P and/or...
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WO/2022/265711A1 |
The present disclosure relates to an apparatus. The apparatus includes a DIMM socket having a seating floor that is to meet both longer length contacts and shorter length contacts of a DIMM when the DIMM is fully seated in the socket, wh...
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WO/2022/265126A1 |
Various embodiments of the present disclosure relate to a method for editing a video by a media processing server in an adaptive media streaming environment. The method therefor may comprise the operations of: receiving a media stream fi...
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WO/2022/260734A1 |
A heat-assisted magnetic recording (HAMR) head has a protective multilayer confined to a window of the disk-facing surface of the slider that surrounds the near-field transducer (NFT) end and write pole end. The protective multilayer is ...
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WO/2022/257033A1 |
A circuit (500) for detecting leakage between word lines (333) in a memory device includes a first and a second coupling capacitor (558-1,558-2). A first terminals (572, 573) of the first and second coupling capacitors (558-1,558-2) are ...
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WO/2022/258146A1 |
A semiconductor device includes at least a first silicon (Si) element (208A) and a second Si element (208B) on a substrate and a ferroelectric layer (212) surrounding the first Si element and the second Si element on at least three sides...
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WO/2022/261197A1 |
Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensati...
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WO/2022/257280A1 |
Provided are a method for preparing a bipolar gating memristor, and a bipolar gating memristor. The method comprises: preparing a lower electrode; depositing a resistive switching material layer on the lower electrode; and depositing an ...
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WO/2022/260692A1 |
A method of programming a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2. For each memory cell group, the ...
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WO/2022/256867A1 |
A data storage medium for storing digital data is disclosed. The medium comprises a mixture of different nano-sized materials, each of the nano-sized materials having a respective optical transition profile characterizing an optical tran...
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WO/2022/256956A1 |
A three-dimensional NAND memory device is provided, comprising a first NAND string including a first channel corresponding to a first cell to be inhibited to program, and a controller configured to control a word line driver and a bit li...
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WO/2022/257764A1 |
A phase change memory (PCM) cell comprises: a first electrode located on a substrate; a phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact wit...
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WO/2022/261582A1 |
Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit...
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WO/2022/259114A1 |
An integrator having an offset evaluation circuit and a collected charge reduction circuitry and method for using the integrator. The integrator includes an amplifier, operable to amplify an input signal, an integration capacitor for col...
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WO/2022/258062A1 |
Provided in the embodiments of the present disclosure are a data writing method for a multi-layer recording medium, and a read-write apparatus therefor. The multi-layer recording medium at least comprises a first recording layer and a se...
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WO/2022/260713A1 |
A data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile me...
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WO/2022/258958A1 |
A nanophotonic nanopore (100) is provided, comprising a nanopore (110) and an optical waveguide (105). The optical waveguide (105) is optically coupled to the nanopore (110) so that a transmission, reflection, emission or absorption prop...
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WO/2022/259653A1 |
A memory cell array unit according to an aspect of the present disclosure comprises a plurality of memory parts arranged in a matrix. Each of the memory parts has a global bit line, a global word line, a memory cell array, a first connec...
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WO/2022/260450A1 |
An audio quality conversion device according to the present invention comprises: a control unit having, mounted therein, an artificial neural network that learns using a plurality of pieces of audio data recorded in recording environment...
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WO/2022/256766A1 |
Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates t...
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WO/2022/252907A1 |
The embodiments of the present application disclose a data interface equalization adjustment method and apparatus, a device and a storage medium, which belong to the technical field of data interfaces. The method comprises: a second devi...
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WO/2022/252099A1 |
Embodiments of the present application relate to the technical field of semiconductors, and provide a magnetic random access memory and a control method therefor, and an electronic device comprising the magnetic random access memory. The...
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WO/2022/253984A1 |
A system (100) for providing a recommended video production (80) is disclosed herein. The system (100) comprises an overview camera (10) for capturing an overview recording, additional camera(s) (15a-n) for capturing additional recording...
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WO/2022/255066A1 |
The recording medium according to one embodiment of the present disclosure is provided with a recording layer. The recording layer includes: an aliphatic polymer; and a multiphoton absorption compound that has a multiphoton absorption pr...
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WO/2022/256398A1 |
A command is transmitted from a mobile computing device to a camera external to the mobile computing device. The command instructs the camera to capture video data of a canine sniff inspection of a parcel. The video data of the canine sn...
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WO/2022/256106A1 |
A computer-implemented method is provided for generating videos from a script read aloud by a user. The method includes: storing a questionnaire; presenting discrete prompts to the user via a user device; recording a user response to the...
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WO/2022/256168A1 |
Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first po...
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WO/2022/256052A1 |
A data storage device and method for legitimized data transfer are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a request from a host for a f...
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WO/2022/256030A1 |
A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program vo...
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WO/2022/252205A1 |
A content addressable memory (CAM) (850) for repairing firmware of multi-plane read operations in a flash memory device is provided. The CAM (850) comprises a set of CAM registers (852) configured to store a mapping table. The mapping ta...
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WO/2022/252987A1 |
The present application relates to the technical field of chips. Disclosed are a method and apparatus for testing a memory chip, which method and apparatus are used for improving the reliability of a determined value of an initialization...
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WO/2022/256050A1 |
Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data stat...
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WO/2022/252120A1 |
In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating ...
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WO/2022/252135A1 |
In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, and a peripheral circuit coupled to the array of memory ce...
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WO/2022/256322A1 |
A dynamic random access memory (DRAM) device includes memory core circuitry and power supply circuitry. The memory core circuitry includes an array of DRAM storage cells, with ones of the DRAM storage cells coupled to wordline and bitlin...
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WO/2022/256123A1 |
Memory bit cells including write control circuits for coupling control of voltage sources to avoid or reduce write contention. The memory bit cells may be static random-access memory (SRAM) bit cells that include a true storage circuit a...
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WO/2022/256169A1 |
Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predet...
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WO/2022/256055A1 |
A data storage device and method for application-defined data retrieval in surveillance systems are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to stor...
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WO/2022/252142A1 |
The present disclosure provides a drive circuit, a display substrate, and a display device. The drive circuit comprises an output circuit, a first node reset circuit, and a second node control capacitor; the output circuit is used for co...
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