| Document |
Document Title |
|
WO/2023/023879A1 |
A magnetic random access memory (MRAM) and an electronic device, which are used for improving the storage density of an MRAM. The MRAM comprises N memory blocks (10(n)), the memory blocks each comprising a plurality of structural cells (...
|
|
WO/2023/025597A1 |
An integrated circuit (160), a system, and a method to integrate phase change memory, PCM, (120) and magnetoresistive random access memory, MRAM, (130) within a same integrated circuit in a system. The integrated circuit may include an M...
|
|
WO/2023/024671A1 |
Embodiments of the present disclosure provide a decoding drive circuit and a method therefor, a word line decoding circuit and a semiconductor memory. The decoding drive circuit comprises at least one decoding drive unit. The decoding dr...
|
|
WO/2023/024101A1 |
Embodiments of the present application provide a ferroelectric memory and a formation method therefor, and an electronic device provided with the ferroelectric memory. The present invention is mainly used for suppressing diffusion of oxy...
|
|
WO/2023/026064A1 |
There is disclosed a computer-implemented method of editing a video file, the method including the steps of: (i) receiving a selection of a video file to edit, the video file including a duration; (ii) presenting a frame of the video fil...
|
|
WO/2023/027443A1 |
The present invention relates to an artificial synapse element using a resistive change memory element based on an amorphous carbon oxide, and a method for manufacturing same, and relates to technology for providing an artificial synapse...
|
|
WO/2023/027495A1 |
A content-addressable memory device according to an embodiment of the present disclosure comprises: a memory cell array including a plurality of memory cells, each having a ferroelectric tunnel field effect transistor (FeTFET); and a mat...
|
|
WO/2023/024083A1 |
Provided in the embodiments of the present disclosure are a spin logic device, a processing-in-memory device, a half adder and a full adder. In the spin logic device, a magnetic unit comprises a spin Hall effect layer and a ferromagnetic...
|
|
WO/2023/026481A1 |
This magnetoresistance effect element comprises: a laminate body including a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic la...
|
|
WO/2023/027070A1 |
Provided is a cover that is applicable in a case where a gasket of a recording device is required to have characteristics that are difficult to be achieved at the same time. A cover 11, which is attached to a base 9 of a recording devi...
|
|
WO/2023/027142A1 |
The purposes of the present invention are to provide a magnetic disk substrate and a magnetic disk capable of maintaining long-term reliability of a hard disk while dealing with an increase in capacity of the hard disk and to provide a m...
|
|
WO/2023/028410A1 |
Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first da...
|
|
WO/2023/023878A1 |
A magnetic random access memory, aimed at increasing the storage density of the magnetic random access memory, and comprising a plurality of structural units and a plurality of auxiliary current lines. The plurality of auxiliary current ...
|
|
WO/2023/025514A1 |
A method for operating an electrically programmable memory cell (2) comprising a chalcogenide for multilevel data memories comprises providing a pulse signal (3) associated with a first predefined temperature level to the memory cell (2)...
|
|
WO/2023/028399A1 |
Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage le...
|
|
WO/2023/024608A1 |
The present disclosure provides a sense amplification structure and a memory architecture, comprising: a first PMOS transistor, a gate electrode being connected to a second complementary sense bit line, and a source electrode being conne...
|
|
WO/2023/028271A1 |
The disclosed computer-implemented method may include initiating a translucent layer, that includes a user interface element, for displaying over a content layer on a computing device, and receiving, from a content source, video content ...
|
|
WO/2023/027788A1 |
A testing apparatus for Devices Under Test (DUTs) includes at least one intake damper and at least one exhaust damper. At least one fan moves recirculated fluid and exterior fluid across one or more DUTs inside the testing apparatus. In ...
|
|
WO/2023/022763A1 |
Disclosed herein are embodiments of a heat-assisted magnetic recording (HAMR) head that includes a near-field transducer (NFT) with a trailing bevel. Also disclosed are sliders and data storage devices comprising those HAMR heads, and me...
|
|
WO/2023/020783A1 |
The present disclosure proposes a method (200) to extend lifespan of an Electronic Control Unit (ECU) and the ECU (100) thereof. The ECU (100) can reside within any anything ranging from vehicles to consumer electronics and performs a pl...
|
|
WO/2023/022767A1 |
A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines t...
|
|
WO/2023/019519A1 |
Provided in the present application are a magnetic device and a manufacturing method therefor, a magnetic memory and an electronic device, which relate to the technical field of magnetic tunneling junctions and can solve the problem of n...
|
|
WO/2023/022299A1 |
The present invention relates to a circuit for sensing a bit-line multi-level voltage for a multi-bit operation of a DRAM including a memory cell for storing data by the operation of a word line and a bit line, the circuit comprising: a ...
|
|
WO/2023/019988A1 |
A data transmission circuit and a memory, which relate to the technical field of semiconductors. The data transmission circuit comprises a sense amplification circuit (10), a first discharge sub-circuit (21), a second discharge sub-circu...
|
|
WO/2023/022765A1 |
A magnetic read-write device includes a disk spindle on which disk media are rotatably mounted, an enclosure in which the spindle is housed, an opening/closing mechanism such as a cover configured for opening to provide access to the spi...
|
|
WO/2023/022766A1 |
Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line vo...
|
|
WO/2023/019545A1 |
Embodiments of the present application provide a chip and a device. The chip comprises a test circuit that is used for transmitting a first test signal to a first interconnect pin by means of a first signal transmission channel; by means...
|
|
WO/2023/020016A1 |
A refresh address counting circuit, a refresh address counting method, a refresh address read-write circuit, and an electronic device, which relate to the technical field of integrated circuits. The refresh address counting circuit compr...
|
|
WO/2023/019561A1 |
A shift register and a driving method therefor, a gate driving circuit and a display apparatus. The shift register comprises: an input circuit, which is configured to input, under the control of a first clock signal, an input voltage int...
|
|
WO/2023/019495A1 |
A memory device includes a memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells includes a selected memory cell connected between a selected bit line and a respecti...
|
|
WO/2023/021452A1 |
The invention relates to a method for protecting a DRAM module (1) against a Rowhammer attack during operation of the DRAM module (1). The DRAM module (1) comprises at least one rank (2), wherein each rank of the at least one rank (2) co...
|
|
WO/2023/019747A1 |
The present invention relates to the technical field of FPGAs. Disclosed is an FPGA capable of implementing data transfer between different configuration application processes. The FPGA internally comprises a hardware memory. A write por...
|
|
WO/2023/022762A1 |
Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stres...
|
|
WO/2023/022241A1 |
The present invention relates to a sound source processing apparatus using a magnetic drum, the apparatus using the magnetic drum to prevent sound quality deterioration and amplify the volume of sound when a sound source transmitted from...
|
|
WO/2023/019658A1 |
The present application relates to the technical field of dynamic memory, and discloses a memory testing method, a device and an apparatus. In the memory testing method, device and apparatus, a command that cannot be directly decoded is ...
|
|
WO/2023/021752A1 |
This memory system is for realizing a reduction in power consumption and an increase in speed of a reading operation of the memory system. The memory system comprises: a source line; a j-layer string selection line; an i-layer first word...
|
|
WO/2023/022505A1 |
Disclosed are: a dynamic random access memory (DRAM) operator which performs a binary neural network (BNN) operation through in-memory computing; and a method for performing a BNN operation through in-memory computing. The DRAM operator ...
|
|
WO/2023/023451A1 |
Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits b...
|
|
WO/2023/019415A1 |
A power-off detection method and a related device. The method is applied to a storage controller (51). The storage controller (51) is coupled to a memory (52), wherein the memory (52) is a non-volatile memory, and a volatile storage unit...
|
|
WO/2023/022298A1 |
The present invention relates to a bitline multi-level voltage sensing circuit for a multi-bit operation of a DRAM including a memory cell that stores data by an operation of a wordline and a bitline, the bitline multi-level voltage sens...
|
|
WO/2023/019997A1 |
Embodiments of the present disclosure relate to the field of semiconductor circuit testing, and in particular, to a test method and a test system. The test method comprises: writing first initial data into a storage module, and an ECC mo...
|
|
WO/2023/019497A1 |
A memory device includes a plurality of memory cell arrays, each memory cell array including a plurality of memory cells connected between word lines and bit lines, a word line driver coupled to the plurality of memory cell arrays and co...
|
|
WO/2023/015640A1 |
A refresh counter circuit, a refresh counting method, and a semiconductor memory. The refresh counter circuit comprises: a first signal generator (310) configured to generate a first carry signal according to each refresh pulse signal ge...
|
|
WO/2023/018454A1 |
An archival data storage system library includes magnetic-recording disk media, a storage enclosure in which the media are housed, data storage devices (DSDs) configured to write to and read from the media, an automated disk handling mec...
|
|
WO/2023/015678A1 |
Provided in the present disclosure are a semiconductor structure and a layout thereof, and a semiconductor device. The semiconductor structure comprises: a plurality of spaced first conductive layers; a plurality of capacitor groups, whe...
|
|
WO/2023/018455A1 |
The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlay...
|
|
WO/2023/018653A1 |
Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes memory core circuitry including an array of DRAM s...
|
|
WO/2023/017638A1 |
A memory module according to one aspect of the present disclosure comprises a plurality of memory cell array units. Each memory cell array unit has a memory cell array in which memory cells are provided one by one at intersections of a p...
|
|
WO/2023/019072A1 |
Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and ...
|
|
WO/2023/018714A1 |
A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense am...
|
