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WO/2023/180859A1 |
The present invention has a first memory cell, a second memory cell on the first memory cell, a first conductor, and a second conductor on the first conductor, the first memory cell and the second memory cell each having a transistor, a ...
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WO/2023/183147A1 |
A power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region and a gate region in the mesa ad...
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WO/2023/178866A1 |
Disclosed herein are a silicon carbide device and a fabrication method therefor. The silicon carbide device comprises: an n-type silicon carbide layer; a plurality of gate trenches located in the n-type silicon carbide layer; a first gat...
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WO/2023/182376A1 |
In this semiconductor device: each of a source that is formed on a main surface of a semiconductor substrate and a floating gate that contacts the main surface with an insulating film therebetween is provided adjacent to a capacitive ele...
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WO/2023/180849A1 |
Provided is a semiconductor device that can be miniaturized or highly integrated. According to the present invention, a semiconductor device includes a metal oxide, a first conductor and a second conductor that are on the metal oxide, a ...
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WO/2023/183215A1 |
A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface ther...
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WO/2023/178895A1 |
A manufacturing method for a silicon carbide device provided by the embodiments of the present application, comprising: forming a hard mask layer on an n-type silicon carbide layer, defining positions of gate trenches by means of a photo...
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WO/2023/181801A1 |
When the thickness of a Si substrate is denoted by dt [cm], the resistance of the Si substrate is denoted by ρs [Ω・cm], the width of each trench is denoted by Wt [cm], the thickness of a first electrode formed on the side surfaces of...
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WO/2023/181749A1 |
In the present invention, a semiconductor device (100) comprises: a substrate (101); a back barrier layer (103); a channel layer (104) having a smaller bandgap than that of the back barrier layer (103); a first barrier layer (105) having...
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WO/2023/181172A1 |
According to the present invention, there is a p layer 1 that is a semiconductor matrix, there is an n+ layer 2 that extends to one side, there is a second impurity layer n+ layer 3 that is in contact with the p layer 1 on the side oppos...
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WO/2023/182822A1 |
Disclosed are a power semiconductor device having a withstand voltage region of a VLD structure, and a method for manufacturing same. The method for manufacturing a power semiconductor device comprises the steps of: deforming an oxide fi...
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WO/2023/178865A1 |
Disclosed is a semiconductor super-junction power device, comprising: an n-type drain region; an n-type drift region located above the n-type drain region; and a plurality of p-type pillars, an electrical charge balance structure being f...
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WO/2023/179993A1 |
A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired con...
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WO/2023/178897A1 |
Embodiments of the present application provide a silicon carbide device terminal structure, comprising: an n-type silicon carbide layer; a first trench located in the n-type silicon carbide layer and at least one second trench located on...
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WO/2023/183495A1 |
A cache circuit for use in a computing system includes at least one random-access memory (RAM) and at least one directory coupled to the RAM. The RAM includes multiple memory cells configured to store data, comprising operands, operators...
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WO/2023/176760A1 |
[Problem] To provide a laminate structure that has excellent crystallinity, a semiconductor device, and methods by which it is possible to produce the same in an industrially advantageous manner. [Solution] The present invention involves...
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WO/2023/173919A1 |
The present application provides a semiconductor device and a preparation method therefor, an integrated circuit, and an electronic device. The semiconductor device comprises a drain electrode, a base substrate, an epitaxial layer, and a...
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WO/2023/175422A1 |
Provided is a semiconductor device comprising a first conductor (233a1), a second conductor (231), a first transistor (201) on a first insulator, and a second insulator (282) on the first transistor. The first transistor comprises a thir...
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WO/2023/176373A1 |
This semiconductor device (10) includes first and second gate portions (24A, 24B) formed of a semiconductor layer containing acceptor-type impurities. First and second gate electrodes (26A, 26B) are disposed on portions of the first and ...
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WO/2023/173482A1 |
A memory, a semiconductor structure and a preparation method therefor, which relate to the technical field of semiconductors. The preparation method comprises: providing a substrate, wherein the substrate comprises an array region and a ...
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WO/2023/173504A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory and a manufacturing method therefor. The semiconductor structure comprises at least one transistor, whi...
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WO/2023/176312A1 |
A semiconductor device (100) for high-frequency amplification according to the present invention is provided with: a substrate (101); a first nitride semiconductor layer (103), a two-dimensional electron gas layer (105) and a second nitr...
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WO/2023/177157A1 |
The present invention relates to a thin film transistor and a manufacturing method therefor, and, more specifically, to a thin film transistor having improved characteristics and a manufacturing method therefor. The thin film transistor ...
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WO/2023/173836A1 |
Disclosed in the present invention are an enhanced GaN-based HEMT device, and a manufacturing method therefor and a use thereof. The composition of the enhanced GaN-based HEMT device of the present invention comprises a substrate, a firs...
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WO/2023/176118A1 |
A semiconductor device (10) is provided with: a semiconductor layer (12); a gate trench (14) that is formed in the semiconductor layer (12) and arranged in a mesh shape in plan view; a field plate trench (42) that is formed in the semico...
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WO/2023/175437A1 |
The present invention provides a semiconductor device which has a high degree of integration. A semiconductor device according to the present invention comprises first and second transistors and an insulating layer. The first transistor ...
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WO/2023/173679A1 |
Embodiments of the present disclosure provide a transistor and a manufacturing method therefor, a memory, and an electronic device. The transistor comprises: a source layer; a semiconductor layer; a drain layer, wherein the source layer,...
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WO/2023/176887A1 |
Provided is a semiconductor device comprising: a first conductive drift region provided in a semiconductor substrate having a front surface and a back surface; and a first conductive buffer region provided closer to the back surface of t...
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WO/2023/176082A1 |
Provided is a MEMS sensor comprising a semiconductor substrate, a sensor portion formed on the semiconductor substrate, a pad portion formed on the semiconductor substrate, and a connection wire which is formed on the semiconductor subst...
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WO/2023/173914A1 |
Disclosed in the embodiments of the present application is a vertical channel transistor structure. Contact layers are respectively introduced between a source electrode and a dielectric layer and between a drain electrode and the dielec...
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WO/2023/176891A1 |
A gate electrode (51) is disposed in a different position from an electric field relaxation layer (40) in the normal direction, and an electrode (73) for an electric field relaxation layer is disposed on an interlayer insulating film (60...
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WO/2023/173425A1 |
Embodiments of the present application provide a structure of and a preparation method for a silicon carbide transistor. The structure of the silicon carbide transistor comprises: a silicon carbide substrate, a first element being doped ...
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WO/2023/175792A1 |
The present invention comprises: a p layer 1 that extends in a direction horizontal to a substrate 20, at a position away from the substrate; an n+ layer 2 that serves as a first impurity layer and that is located on one side of the p la...
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WO/2023/175820A1 |
The present invention provides a method for producing a semiconductor device, the method comprising: a step in which a first insulating film (20) that has a first opening (20a) is formed; a step in which a first resist (24) that has a se...
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WO/2023/176907A1 |
Provided is a semiconductor device that comprises: a base region of a second conductivity type that is disposed between a drift region and an upper surface of a semiconductor substrate; a first lifetime region that is disposed in a drift...
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WO/2023/176150A1 |
In the present invention, a pixel transistor is positioned in a pixel-separating trench of a solid-state imaging device. The solid-state imaging device comprises the trench and the pixel transistor. The trench separates the pixels. The...
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WO/2023/176759A1 |
[Problem] To provide: a layered structure having excellent crystallinity; a semiconductor device; and a manufacturing method by which such structure and device can be obtained in an industrially advantageous manner. [Solution] In the pre...
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WO/2023/176591A1 |
A sintered body of an oxide containing an In element, a Ga element, and an Al element, wherein the atomic compositional ratio of the In element and the Al element satisfies formula (1) and formula (2). [In]/([In]+[Ga]+[Al])>0.70 … (1...
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WO/2023/176744A1 |
The present invention relates to a GaN epitaxial substrate comprising: a GaN substrate; and a GaN buffer layer epitaxially grown on the GaN substrate, wherein: the GaN epitaxial substrate includes a point A that exists in the GaN substra...
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WO/2023/173507A1 |
A TFT substrate and a manufacturing method therefor, a liquid crystal display panel, and an OLED display panel. A source electrode (61) and a drain electrode (62) of the TFT substrate are both obtained by etching a conductive layer (50)....
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WO/2023/176932A1 |
This semiconductor device comprises a semiconductor substrate of a first conductivity type, a semiconductor layer of the first conductivity type, a first electrode, a second electrode, a first trench, a second trench, an insulating layer...
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WO/2023/173335A1 |
Provided in the present application are a silicon carbide power device and a preparation method therefor, and a power conversion module. The silicon carbide power device comprises a silicon carbide substrate, an epitaxial layer and an oh...
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WO/2023/175436A1 |
The present invention provides a semiconductor device which comprises a transistor of a very small size. A semiconductor device according to the present invention comprises a transistor, a first insulating layer and a second insulating l...
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WO/2023/176260A1 |
This semiconductor device (100) comprises a substrate (101), a buffer layer (102), an intermediate layer (103), an electron transport layer (104), an electron supply layer (105), a source electrode (201) and drain electrode (202), and a ...
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WO/2023/176056A1 |
A semiconductor device (1A) according to the present invention comprises: a chip (2) which has a main surface (3); a first inorganic film (27) which contains an insulator and covers the main surface; a second inorganic film (41) which co...
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WO/2023/174610A1 |
In at least one embodiment, the method is for producing a power semiconductor device (1) and comprises the following steps: - providing a semiconductor body (2) based on SiC, - irradiating at least a first portion (21) of a top side (20)...
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WO/2023/168749A1 |
Provided in the present application are an array substrate and a display panel. The display panel comprises an array substrate. An ion implantation barrier layer in the array substrate and at least part of a channel portion of an active ...
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WO/2023/170270A1 |
The present invention relates to a ceramic substrate comprising: aluminum oxide (AI2O3) with an average grain size between 1.31 and 1.55 μm; Zirconium dioxide (ZrO2) with an average grain size between 0.65 and 0.75 μm, Yttrium oxide (Y...
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WO/2023/168897A1 |
Provided in the present disclosure are a semiconductor structure and a preparation method therefor. The preparation method for a semiconductor structure provided by the present disclosure comprises the following steps: providing a substr...
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WO/2023/171137A1 |
This semiconductor device comprises a vertical field effect transistor having a low impurity concentration layer (33), a body area (18), a gate trench (17) that extends in a first direction parallel to the top surface of the low impurity...
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