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WO/2023/168752A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory and a manufacturing method therefor. The semiconductor structure comprises at least one transistor. The...
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WO/2023/171454A1 |
This semiconductor device includes: a semiconductor layer that has a surface; a source region and a drain region that are positioned on the surface, separated in a first direction, as viewed from the thickness direction which is perpendi...
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WO/2023/168807A1 |
The embodiments of the present disclosure provide a semiconductor structure and a method of forming same. The semiconductor structure comprises: a gate dielectric layer; and a gate electrode located on a surface of the gate dielectric la...
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WO/2023/168570A1 |
A method for partially forming dielectric isolation for a gate-all-around device, the method comprising: providing a substrate (101), and forming a fin structure and a surrounding stacked member (104) on the substrate (101), the surround...
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WO/2023/170511A1 |
A semiconductor device having a high storage density is applied in the present invention. The semiconductor device includes a first insulator, a first layer, a second insulator, a second layer, a third insulator, and a third layer layere...
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WO/2023/170782A1 |
In the present invention, a first insulating layer 21 is provided on a substrate 20. Separate from the insulating layer are: a plurality of first impurity layers n+ layers 2 set apart in the horizontal direction and vertical direction wi...
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WO/2023/171134A1 |
[Problem] To provide a semiconductor device that has a structure suited for miniaturization and that is capable of achieving high-voltage resistance. [Solution] A semiconductor device comprises: an SJ layer which extends in a first direc...
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WO/2023/170732A1 |
The purpose of the present invention is to provide a plasma processing method which is highly controllable and is capable of selectively removing a metal-containing layer. The purpose is achieved by a plasma processing method that plasma...
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WO/2023/171438A1 |
This nitride semiconductor device comprises: an electron supply layer; a gate layer; a gate electrode; a passivation layer; a source electrode; a drain electrode; an active region; and an inactive region that is adjacent to the active re...
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WO/2023/171502A1 |
Corrosion resistance, oxidation resistance, and high-temperature strength are secured for a semiconductor substrate of SiC, while also achieving a reduction in production costs, by: forming a molding 20 by layering a paste comprising SiC...
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WO/2023/172794A1 |
Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include...
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WO/2023/172279A1 |
A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming fi...
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WO/2023/170755A1 |
In the present invention, a memory device comprises a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in plan view, said memory device controlling the voltage applied to a first ga...
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WO/2023/172578A1 |
A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the ch...
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WO/2023/169592A1 |
Provided are a MOSFET device and a manufacturing method therefor. An embodiment comprises: first forming a first implant area which is easy to diffuse, and then sequentially forming a second implant area which is not easy to diffuse and ...
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WO/2023/171147A1 |
Provided is a semiconductor device in which it is possible to suppress both short channel and variations in transistor characteristics. This semiconductor device comprises a semiconductor substrate and a field effect transistor provided ...
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WO/2023/171139A1 |
This semiconductor device comprises: a semiconductor layer having a first surface and a second surface on the opposite side from the first surface; a bottom gate region of a first conductivity type formed in the semiconductor layer; and ...
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WO/2023/172280A1 |
A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removin...
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WO/2023/171402A1 |
A storage device (500) according to an embodiment of the present disclosure comprises: a first memory (501) that allows data reading/writing; a second memory (502) that allows data reading/writing; a detection unit (504) that detects mag...
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WO/2023/171431A1 |
A detection device provided with: a substrate; a plurality of photodiodes, which are arranged on the substrate and in each of which a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and an upper electrode a...
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WO/2023/170738A1 |
This magnetization rotating element comprises a spin-orbit torque wire and a first ferromagnetic layer connected to the spin-orbit torque wire, wherein the spin-orbit torque wire includes an amorphous structure, and the amorphous structu...
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WO/2023/171138A1 |
[Problem] To provide a semiconductor device which makes it possible to improve withstand voltage performance while having a further compact structure. [Solution] A semiconductor device comprising: a source region that is of a first condu...
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WO/2023/166827A1 |
A semiconductor device according to the present invention comprises: a semiconductor chip that has a first main surface; a withstand voltage holding structure that is formed in the peripheral region in the periphery of an element formati...
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WO/2023/168138A1 |
Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate...
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WO/2023/164911A1 |
Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact cou...
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WO/2023/167749A1 |
A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region (644) can be formed by implanting a sidewall of a body region (7...
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WO/2023/165113A1 |
A storage unit and a manufacturing method therefor, and a semiconductor device. The storage unit comprises: a conductive substrate, which has an upper surface, wherein a first hole is located in the conductive substrate; the first hole, ...
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WO/2023/167147A1 |
This silicon carbide semiconductor device comprises: an n-type drift region; a p-type body region; an n-type source region; a p-type contact region; a gate trench that extends in a first direction; a gate insulating film; a gate electrod...
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WO/2023/166377A1 |
Provided is a storage device that enables miniaturization or high integration. This storage device comprises: a memory cell that includes a capacitive element and a transistor on the capacitive element; a first insulator on the capacitiv...
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WO/2023/167161A1 |
In the present invention, a second MOSFET comprises: a body region; a drain region extending in the y direction; a first well region formed away from the drain region in the x direction; a gate electrode formed on a gate insulating film ...
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WO/2023/166378A1 |
Provided is a semiconductor device capable of being miniaturized or highly integrated. This semiconductor device has first and second transistors, and a capacitor. The first transistor is provided in the same layer as the second transist...
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WO/2023/166608A1 |
According to the present invention, Si base materials 24aa-24ad, 24ba-24bd and 45a-45d are arranged to be adjacent to each other in the horizontal direction at regular intervals, while being parallel to a substrate 20. In addition, gate ...
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WO/2023/165000A1 |
The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure comprises: a substrate having a first area and a second area; a first gate structure locate...
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WO/2023/167083A1 |
Provided is an effective structure for an electrostatic discharge (ESD) protection circuit in which a nanosheet device is used. A device structure (21) that constitutes one of an anode or a cathode is disposed opposite a device structure...
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WO/2023/165341A1 |
A channel etching method, comprising providing an object to be etched, and after the object to be etched is subjected to primary etching, alternately performing surface treatment and secondary etching until sacrificial layers of all fin ...
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WO/2023/164813A1 |
A source/drain confined epitaxy method for a gate-all-around device, the method comprising: forming on a substrate (105) several fin structures which are arranged in a first direction, and forming on the several fin structures several du...
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WO/2023/166374A1 |
Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device is provided with a memory cell having a transistor and a capacitor. Either the source electrode or the drain electrode of the tran...
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WO/2023/165242A1 |
Disclosed in the present application are a SiC MOSFET and a preparation method therefor, and an integrated circuit. In the SiC MOSFET, a gate electrode is located at two sides of a fin-shaped channel layer. Arranging the gate electrode a...
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WO/2023/166379A1 |
Provided is a novel semiconductor device. In the semiconductor device, a lateral channel transistor and a vertical channel transistor are combined. A p-channel transistor is composed of the lateral channel transistor, and an n-channel tr...
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WO/2023/164821A1 |
The semiconductor device includes a substrate, a first and a second nitride-based semiconductor multiple layered structures, a first and a second conductive layers. The substrate has a device region and a peripheral region that encloses ...
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WO/2023/166666A1 |
This semiconductor device comprises: a field insulating film (10) that contacts a first gate electrode (9) formed in a termination trench (7) and is formed from the inside to the outside of the termination trench (7) while covering the t...
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WO/2023/166707A1 |
This neuromorphic device has a plurality of paired elements, and a control device that controls each of the plurality of paired elements. Each of the plurality of paired elements includes a first magnetoresistive element, a second magnet...
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WO/2023/165283A1 |
Provided in the embodiments of the present application are a memory having a tunneling field effect transistor (TFET), and an electronic device comprising the memory which has the TFET. The present application relates to the technical fi...
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WO/2023/166657A1 |
The present invention inhibits electric potential variation during a switching operation and prevents an increase in switching loss. This semiconductor device comprises: a first semiconductor layer; a gate trench; a first well region; a ...
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WO/2023/161383A1 |
An integrated circuit (IC) device configured for voltage reduction between an input and an output comprises a plurality of alternatingly doped regions arranged laterally in a lateral direction and alternatingly doped with dopants of oppo...
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WO/2023/163855A1 |
Self-aligned FET devices and associated fabrication methods are disclosed herein. A disclosed process for forming a FET includes forming a first mask, implanting a deep well region in a drift region using the first mask, forming a spacer...
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WO/2023/159390A1 |
Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a source and a drain, each having a first doping type; a gate located between the source and ...
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WO/2023/163023A1 |
Provided is a composition containing a quantum dot material having a perovskite crystal structure and an olefin polymer. The olefin polymer is preferably a cyclic olefin polymer or a block copolymer containing repeating units derived fro...
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WO/2023/164157A1 |
Apparatuses, systems, and methods are disclosed for an integrated circuit (100) with 2D field-effect transistors (110) and on-chip thin film layer deposition with electrical characterization. A corresponding layer structure and manufactu...
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WO/2023/162448A1 |
The present invention is a radio-frequency device substrate characterized by comprising: a support substrate which has an uneven surface; a diamond layer on the surface of the support substrate; and a silicon oxide film layer on the diam...
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