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WO/2011/161860A1 |
Disclosed is a frequency synthesizer, comprising a control circuit (20) that generates a digital control signal; and a Digitally Controlled Oscillator (10) wherein an oscillation frequency changes according to the generated digital contr...
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WO/2011/159719A2 |
Disclosed is a proportional controller that utilizes a deflected metal cantilever (410) that provides a progressive change in capacitance for a given deflection that is used to generate a proportional control signal. In addition, a effic...
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WO/2011/158576A1 |
Disclosed is an oscillation circuit comprising a capacitor, a charge and discharge unit for switching between charging and discharging of the capacitor according to a control signal, a comparator for comparing the voltage of the capacito...
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WO/2011/156393A2 |
These various embodiments serve to facilitate interlaced amplitude pulsing using a hard-tube type pulse generator having at least one energy-storage unit each comprising at least one energy-storing capacitor. Generally speaking, this com...
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WO/2011/154778A1 |
A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a fu...
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WO/2011/155532A1 |
A flip-flop circuit (FF10) related to the present invention is provided with master latch circuits (LAT11 and LAT12), slave latch circuits (LAT13 and LAT14), C-element circuits (CE11 to CE14), and inverter circuits (INV11 to INV14). The ...
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WO/2011/150502A2 |
Disclosed herein is a functional electrical stimulation (FES) device and system. In one embodiment, sequential bipolar pulse stimulation may be provided to an area of a living body via one or more electrode leads applied to the area via ...
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WO/2011/136964A1 |
A level shifter (400) and method are provided for balancing rise and fall times of a signal. An input circuit (420, 413) receives a differential logic signal (Inp, Inn) with two complimentary logic levels. A level transition balancing ci...
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WO/2011/127685A1 |
A boost DC/DC converter and a logic controlling circuit thereof. The logic controlling circuit (300) is used to regulate pulse width modulation (PWM) signals of the boost DC/DC converter. The logic controlling circuit includes a judging ...
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WO/2011/125566A1 |
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal outpu...
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WO/2011/126896A1 |
A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly...
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WO/2011/127023A1 |
Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a se...
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WO/2011/123451A1 |
A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit 200 includes a first linear feedback shift register 204 and a second linear feedback shift register 206. The first ...
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WO/2011/119746A1 |
Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a f...
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WO/2011/115531A1 |
The invention relates to the field of medical technology, specifically to defibrillators, and can be used in medical institutions for reanimation, cardio surgery and intensive therapy departments and for departments of emergency aid, and...
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WO/2011/115888A2 |
A rail-rail comparator having an input stage with independent positive and negative differential voltage offset compensation tracks changes in Gm (transconductance) of the input stage. By tracking the changes in Gm (transconductance) of ...
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WO/2011/112579A2 |
A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of ...
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WO/2011/107828A1 |
An integrated circuit (100) comprises clock gating circuitry (140) comprising at least one gating component (210, 220) located within a clock distribution network (120) and arranged to enable at least one part of the clock distribution n...
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WO/2011/108345A1 |
A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit are provided. A clock signal is supplied to one of transistors connected to a first output terminal. A power supply ...
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WO/2011/108343A1 |
An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor ...
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WO/2011/032149A9 |
A high-voltage bipolar rectangular pulse generator using a high efficiency solid-state boosting front-end and an H-bridge output stage is described. The topology of the circuit generates rectangular pulses with fast rise time and allows ...
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WO/2011/095901A1 |
A comparator circuit has a switching arrangement between first and second input branches. Second transistors of the first and second input branches (which would normally be the main current mirror transistors in a conventional comparator...
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WO/2011/092759A1 |
Disclosed is a flip-flop circuit (200) having improved operating speed. The flip-flop circuit (200) comprises: a first logic circuit (204) wherein a selection signal (SA) and a clock signal (CK) are inputted, and which generates a first ...
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WO/2011/092668A1 |
An electromagnetic pulse generating apparatus including an elongated flexible tube having an inflated mode and a non-inflated mode, wherein a cross section of said tube perpendicular to the elongation axis is larger when inflated mode th...
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WO/2011/089847A1 |
It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element includin...
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WO/2011/089918A1 |
Disclosed are a PLL circuit and an injection-locked frequency divider that can lessen the effect of parasitic capacitance and wherein the operating frequency is broadband. The injection-locked frequency divider (100) is provided with: a ...
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WO/2011/086688A1 |
A bit sequence generation device (200) is provided with a glitch generation circuit (205) for generating glitches; a sampling circuit (220) for sampling glitch waveforms generated by the glitch generation circuit (205); and a glitch form...
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WO/2011/084087A2 |
The invention relates to contact weapons and remote weapons with electrical means for hitting a target (electroshock weapons), as well as to technology for producing high-voltage electrical pulses at a high current. The high-voltage puls...
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WO/2011/085139A2 |
A random number generator comprises a first high frequency (HF) oscillator, a second low frequency (LF) oscillator, a delay buffer, a multiplexer, and a sampling circuit. The HF oscillator generates a high frequency oscillating signal. T...
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WO/2011/081767A1 |
A signal generating circuit (600) and method are disclosed that do not require a phase- locked- loop and a low frequency temperature- stable oscillator. The method may include generating an oscillating output signal (602) (Ik) responsive...
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WO/2011/081951A1 |
Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and ...
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WO/2011/078373A1 |
An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which...
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WO/2011/077908A1 |
An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input t...
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WO/2011/074408A1 |
A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a seco...
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WO/2011/074050A1 |
Provided is a latch circuit comprising a latch unit and a clock propagation suppressing unit. The latch unit holds and outputs inputted data of 0 or 1. The clock propagation suppressing unit compares input data inputted to the latch unit...
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WO/2011/072081A1 |
A quadrature output (IP, IN, QP, QN) high-frequency RF divide-by-two circuit (129) includes a pair of differential complementary logic latches (142, 143). The latches are interconnected to form a toggle flip-flop (200). Each latch (200) ...
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WO/2011/068928A1 |
A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock s...
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WO/2011/063974A1 |
It is described a driving circuit (1) having at least one output terminal (OUT) connected to an ultrasonic pulse generator circuit and providing thereto with an output voltage (Vout), characterized in that it comprises at least one first...
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WO/2011/065685A2 |
The present invention relates to an oscillator circuit which compensates for external supply voltage, temperature and process, and comprises: an external supply voltage (VDD) and a reference voltage generating unit (310) which generates ...
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WO/2011/062075A1 |
To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically ...
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WO/2011/063119A1 |
Embodiments relate to methods and devices comprising an optical pipe comprising a core and a cladding. An embodiment includes obtaining a substrate comprising a photodiode and a first protective layer, the first protective layer having a...
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WO/2011/055103A1 |
A clock arrangement to provide clock signals in an integrated circuit are disclosed. The clock arrangement comprises a conductive signal path formed as a non-inverting closed loop (10), a drive circuit (30) for generating phase-shifted o...
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WO/2011/052383A1 |
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal...
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WO/2011/047861A1 |
Ring oscillator comprising a plurality of elementary units (5) connected in cascade and linked in order to make a chain with the respective output terminals (OUT) connected to the input terminals (IN) of the successive elementary units (...
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WO/2011/045280A1 |
The invention relates to an oscillator, and to a method for generating electric oscillations depending on a frequency control signal having a transfer oscillator circuit for generating the electric oscillations and a control loop for reg...
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WO/2011/038788A1 |
The present invention relates to a method of generating a hole or recess or well in an electrically insulating or semiconducting substrate, and to a hole or recess or well in a substrate generated by this method. The invention also relat...
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WO/2011/039846A1 |
Disclosed is a random number generation circuit which generates random numbers. The random number generation circuit is provided with: an oscillation circuit having an amplifier row, which has a plurality of amplifiers connected in serie...
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WO/2011/036212A1 |
The present invention relates to a static frequency divider circuitry comprising a delay flip-flop related structure. An object of the present invention is to design a frequency divider circuitry that meets upcoming low power requirement...
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WO/2011/034862A1 |
A latching element (124) latches incoming data (D(7:0)) into an integrated circuit (101). The latching element (for example, a latch or flip-flop) can be considered to include a data path portion (126), a clock path portion (127), and an...
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WO/2011/031190A2 |
The invention pertains to the field of electrical engineering, and particularly relates to techniques and equipment for accumulating electrical energy in large amounts with low weight-dimension indices. The technical result consists in t...
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