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WO/2009/110086A1 |
In a latch circuit with scan (1), main latch circuits (Masters 1-4) corresponding to data inputs (D1-4) are connected in series, in the main latch circuits (Masters 4) of stages other than a last stage, the scan output of their own circu...
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WO/2009/104358A1 |
A plurality of multistage delay circuits (MD1 to MD5) each have n output terminals (n is a natural number). Each of the multistage delay circuits (MD1 to MD5) delays the input signal and outputs n delayed signals with different delay tim...
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WO/2009/104129A2 |
An electronic circuitry based on current-mode logic is provided which comprise a logic unit (LP) having a plurality of latch logic units (L1, L2, LN) each with a hold node (H1 - HN) and a sample node (S1 - SN) and a clock unit (CP) havin...
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WO/2009/101015A1 |
A digitally controlled oscillator comprising: an oscillator core configured to output an adjustable frequency output; and an oscillator tuner comprising at least one switchable impedance stage configured to control the oscillator core fr...
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WO/2009/099499A2 |
A circuit (10) has first latch (30), a second latch (32), a coupling circuit (39), and a power down circuit (34). The first latch (30) has an input/output coupled to a data node (27). The second latch (32) has an input/output. The coupli...
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WO/2009/097315A1 |
In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The met...
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WO/2009/095717A1 |
An improved regenerative clocked sampling circuit is described which uses a single clocking signal to switch the circuit between a tracking phase in which the state tracks the input signal, and a bistable phase during which the state rap...
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WO/2009/091287A1 |
The invention relates to radio engineering and experimental medicine. The aim of the invention is to extend functionalities of an N-frequency harmonic and pulse signal generator by ensuring the operation thereof in a broad-band range wit...
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WO/2009/089403A1 |
A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of t...
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WO/2009/084524A1 |
Provided is a random number generation mechanism based on a normal distribution not causing a sequence correlation. The random number generation mechanism based on a normal distribution includes: a random recurrence plot generation mecha...
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WO/2009/078242A1 |
A non-volatile latch circuit comprises a latch circuit (11), first and second magnetoresistive elements (13-1, 13-2), and a current supply section (12). The latch circuit (11) temporarily holds data. The first and second magnetoresistive...
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WO/2009/078118A1 |
A magnetic path is formed by a magnetic detector (24) or (26) (more specifically, a magnetic wire (70)), the magnetic pole of a magnet (22), and a rotating shaft (20) as a motor rotates. Since the magnetic wire (70) consists of a magneti...
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WO/2009/073556A1 |
Devices and methods are provided for boosting a battery voltage and driving an actuator with programmable voltage shapes. In one embodiment, there is provided a device (e.g., an actuator driver) that includes: a boost circuit coupled to ...
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WO/2009/072511A1 |
A non-volatile latch circuit comprises first and second inverters connected in a cross-coupled configuration so as to hold one-bit data, first and second magnetoresistive elements each having first to third terminals, and a current suppl...
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WO/2009/072268A1 |
A delay circuit (100) includes a MOSFET (1) and bias voltage sources (12a, 12b). The bias voltage sources (12a, 12b) apply voltage across a drain and a source of the MOSFET (1). The bias voltage source (12a) supplies a source voltage Vss...
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WO/2009/069597A1 |
Both high speed and high reliability in synchronization with a clock signal are balanced. A synchronization device for inputting an asynchronous signal and a clock signal and outputting a synchronous signal synchronized with the clock si...
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WO/2009/068164A1 |
The present invention relates to a circuit and a method for operating a consumer (10) comprising a power source (1) for providing a power supply to a consumer (10). A first switch (7) connected in parallel to a series circuit comprising ...
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WO/2009/066765A1 |
To generate a pulse signal having a desired pulse width. There are included a ring oscillator circuit including a plurality of series-connected delay circuits; rising and falling signal generating parts each of which is connected to a re...
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WO/2009/063948A1 |
An M-sequence generating circuit, which is applicable to a random error generating apparatus, has a plurality of registers that are cascade connected and a plurality of exclusive-OR gates that feed bit data stored in the respective regis...
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WO/2009/063542A1 |
A semiconductor device is characterized in that it includes latch circuits (103, 104) each having a plurality of data retention nodes, a first capacitive element (C) connected to the first data retention node (A) included in the pluralit...
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WO/2009/060625A1 |
A nonvolatile latch circuit comprises a latch circuit (6), output terminals (8, 9) of two inverters constituting the latch circuit, a first inverter (INV1) connected with one end of the operating current passage of one inverter, a second...
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WO/2009/062130A2 |
Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel tran...
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WO/2009/058995A2 |
The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse gene...
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WO/2009/054183A1 |
Intended is to prevent the overheat of a spin valve element. Provided is a driving method for feeding the spin valve element with a drive current thereby to acquire an oscillating signal. The driving method comprises the step of subjecti...
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WO/2009/044993A1 |
Provided are an ultra wideband (UWB) system and a method for operating the same. The UWB system includes a baseband unit for modulating/demodulating an impulse data signal and generating a power management control signal using burst hopp...
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WO/2009/042615A1 |
Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forw...
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WO/2009/037831A1 |
In a double edge trigger type of flip-flop circuit (200), a first latch circuit (10) latches an input data at one of the rising and falling edges of a clock signal. A second latch circuit (20), which is connected in parallel with the fir...
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WO/2009/037770A1 |
A memory circuit comprises a first latch circuit and a second latch circuit into which input data is written with clock signal timing and which retains the written data, a data input circuit for inputting data to the first latch circuit ...
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WO/2009/038846A2 |
A bipolar pulse forming transmission line module and system for linear induction accelerators having first, second, third, and fourth planar conductors which form a sequentially arranged interleaved stack having opposing first and second...
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WO/2009/032380A2 |
Certain branched carboxylic acids may serve as improved lubricity additive compositions in distillate fuels, and in particular for cold weather applications. Suitable branched carboxylic acids may include, but are not necessarily limited...
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WO/2009/027468A2 |
An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second su...
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WO/2009/029713A1 |
A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes ...
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WO/2009/028717A1 |
A large number of random numbers (particularly, true random numbers) essential to the ciphering technology and authentication technology are quickly and stably generated. Counters are provided for respective random pulse generators. Each...
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WO/2009/024717A2 |
The invention relates to a test device (20) for an analog circuit (12) to be mounted on a mixed circuit (10) including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator (22) connected ...
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WO/2009/025346A1 |
A data holding device comprises a loop structure part (LOOP) that holds data by use of logic gates connected in a loop (e.g., inverters INV3 and INV4 of Fig. 1); a nonvolatile storage part (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a and Q2b) ...
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WO/2009/025327A1 |
Four stochastic resonators (20-1)-(20-4) to output a pulse signal in accordance with a stochastic resonance phenomenon are unidirectionally coupled in a ring-like form to constitute a fluctuation oscillator (10). When a signal output fro...
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WO/2009/022275A1 |
The present invention relates to a level shifter circuit (20) for transistors requiring high voltage, such as nonvolatile memories. In the circuit configuration, the drain- to-source voltage across the NMOS transistors (Ql, Q4) can be su...
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WO/2009/023719A2 |
A square-function circuit (10) includes an input field-effect transistor (FET) (12) having a gate that is driven by an input voltage (V1N, V1N2) and is configured to conduct an output current (IOUT)- The circuit also includes a feedback ...
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WO/2009/019743A1 |
A ring oscillator having the odd number of inversion selection circuits connected in an annular form. Each of the inversion selection circuits has a first input to which the output from the inversion selection circuit in a previous stage...
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WO/2009/017654A1 |
The invention is a method and circuit for generating a pulsed periodic signal comprising a sub-harmonic mixer (101 ) and a control circuit (103) adapted to cause the output signal of the sub-harmonic mixer (101) to be pulsed. A pulsed ra...
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WO/2009/014747A1 |
A charge pump circuit comprising a plurality of charge pumps with outputs connected In parallel, an oscillator providing a plurality of out of phase clock signals, further comprising a first capacitor in each charge pump charged by a swi...
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WO/2009/013301A1 |
An electronic device, comprises a digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator is provided for comparing the voltage drop across the varia...
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WO/2009/003068A1 |
A level shifter (100) includes an inverting circuit (104), a cross-coupled level shifting latch (102), and a SR logic gate latch (103). The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inp...
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WO/2008/153777A2 |
An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source cou...
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WO/2008/152085A1 |
The present invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and afirst bi-stable element being adapted to be switched in response...
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WO/2008/148657A1 |
The invention relates to a method for the production of a ceramic spiral pulse generator, comprising the following steps: a) Providing a film composite made of at least one ceramic green film and at least one metal layer, b) winding the ...
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WO/2008/145631A2 |
The invention relates to a compact high-voltage pulse generator based on a spiral pulse generator, wherein the spiral pulse generator is configured as an LTCC component and wound of at least two ceramic foils and metal layers applied the...
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WO/2008/142735A1 |
A device generates k-bit parallel pseudo random data using n pieces of first to n-th (n is an integer ≥3) registers and k pieces of first to k-th (k is an integer ≥2) exclusive OR circuits. An output from the m-th register (m is an i...
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WO/2008/142488A1 |
Novel random number generation methods and novel random number generators based on continuous-time chaotic oscillators with dual oscillator architecture are presented. Numerical and experimental results not only verify the feasibility of...
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WO/2008/139239A1 |
An apparatus for communicating via a medium while affecting the strength and/or direction of an electric field experienced by the medium is provided. The apparatus includes signal guiding means for guiding a signal. The signal guiding me...
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