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Patent Searching and Data


Matches 1 - 50 out of 7,034

Document Document Title
WO/2022/160036A1
A method for connecting a plurality of remotely located users over a shared environment. The method includes the steps of loading, by a first user, a first data sample to a shared sequencer, which is converted to a base64 string. The bas...  
WO/2022/150058A1
In one embodiment, multiplier circuitry multiplies operands of a first format. One or more storage register circuits store digital bits corresponding to an operand and another operand of the first format. A decomposing circuit decomposes...  
WO/2022/142157A1
Disclosed are a double-buffering encoding system and a control method therefor, and a medium and a device. The double-buffering encoding system comprises: a production module, a consumption module and two buffering modules, wherein the p...  
WO/2022/133718A1
A number of domain specific accelerators (DSA1-DSAn) are integrated into a conventional processing system (100) to operate on the same chip by adding additional instructions to a conventional instruction set architecture (ISA), and furth...  
WO/2022/126621A1
A reconfigurable processing element array for zero-buffer pipelining, and a zero-buffer pipelining method. In a reconfigurable processing element array (PEA) for zero-buffer pipelining, data transmission between processing elements (PE),...  
WO/2022/105252A1
The present disclosure relates to a computing core, a computing chip, and a data processing device. The computing core comprises an input module configured to receive data blocks, a computing module configured to perform a hash operation...  
WO/2022/104452A1
A machine vision functionality deployment system for transcoding a raw machine vision data signal in an existing machine vision system for capturing sensed information from a substrate. Provided is a digital data interface bus to: receiv...  
WO/2022/108686A1
Various embodiments of methods and systems for a modem-directed application processor (111) boot flow in a portable computing device ("PCD") (102) are disclosed. An exemplary method includes an application processor (111) that transition...  
WO/2022/099406A1
A method for populating an electronic health record, and a system configured to perform this method, comprises a step of analyzing captured raw data to classify the same according to type of health information to which it pertains; and a...  
WO/2022/097902A1
An electronic device and a control method therefor are disclosed. The electronic device of the present disclosure may comprise: a memory for storing first input data and first weight data used for the operation of a neural network model;...  
WO/2022/083060A1
A processing method for a FIFO memory. The FIFO memory comprises a data caching module and an address control module. The processing method comprises: an address control module receives an empty/full state signal of a data caching module...  
WO/2022/086532A1
An example system includes: a print queue address engine to register network addresses of print queue devices in an index; a print request receive engine to: receive, from a client device, a request to validate printing of a print job at...  
WO/2022/078264A1
A shift saturation processing method and an application thereof, the steps comprising: performing an XNOR operation on every bit of data to be shifted and a most significant bit thereof, selecting all bits in the data to be shifted which...  
WO/2022/078263A1
A shift and saturation synchronous processing method, comprising the following steps: generating a shift MASK, generating a selection signal of an overflow bit after a shift, marking a bit corresponding to a shift overflow as 1, and mark...  
WO/2022/072802A1
Systems and methods for lossless compression of tabular numeric data are provided. The system can include one or more data compression servers executing data compression system code to compress the tabular numeric data, a storage databas...  
WO/2022/034388A1
An aspect of the invention provides a method of transmitting data over a wireless network. The method includes maintaining a plurality of data packets within a first buffer and encoding at least some of the data packets within the first ...  
WO/2022/033174A1
A first in first out (FIFO) memory and a storage device. The FIFO memory comprises: a plurality of memory cells, an output of each memory cell is connected to the same node; the memory cell comprises memory sub-cells, a selector, and a d...  
WO/2021/259230A1
The embodiments of the present application disclose an inter-module communication method and system. The inter-module communication method is used for controlling data transmission between a first memory, a second memory and an FIFO comm...  
WO/2021/245164A1
Low-cost time synchronization associated wireless Battery Management System (BMS) and a host controller are described herein. The time synchronization techniques described herein are low-cost because of the use of existing communicating ...  
WO/2021/232843A1
Provided are an image data storage method, an image data processing method and system, and a related apparatus. The image data processing method comprises the following steps: sequentially storing image data in a dynamic random memory ac...  
WO/2021/236252A1
Compression of data that permits direct reconstruction of arbitrary portions of the uncompressed data. Also, the direct reconstruction of arbitrary portions of the uncompressed data. Conventional compression is done such that decompressi...  
WO/2021/221708A1
Detection of typed and/or pasted text, caret tracking, and active element detection for a computing system are disclosed. The location on the screen associated with a computing system where the user has been typing or pasting text, poten...  
WO/2021/185262A1
A computing apparatus (402) for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing apparatus (402) may be comprised in a combined processing apparatus (40...  
WO/2021/141827A1
Embodiments of the disclosure provide method for performing contraction on a tensor network. The method can include: receiving, by a system, a tensor network comprising a plurality of tensors and a plurality of edges among the plurality ...  
WO/2021/134050A1
An electronic device includes a queue with multiple sub-queues arranged in a logical hierarchy from a lowest sub-queue to a highest sub-queue, each sub-queue including a separate subset of a set of entries of the queue, and a separate ag...  
WO/2021/105648A1
Data processing apparatuses, methods of data processing, complementary instructions and programs related to ring buffer administration are disclosed. An enqueuing operation performs an atomic compare-and-swap operation to store a first p...  
WO/2021/101451A1
Disclosed are a method and apparatus for storing data. The method includes: acquiring data to be stored; converting the data to be stored from an initial data type to a target data type, a data length corresponding to the target data typ...  
WO/2021/092352A1
Systems, methods, and computer program product embodiments are disclosed for removing any fixed frequency interfering signal from an input signal without introducing artifacts that are not part of the original signal of interest. An embo...  
WO/2021/081181A1
A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit ...  
WO/2021/067312A1
Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending ...  
WO/2021/050286A1
Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command (610) from a bus master coupled to the serial bus, determining that a sequence is being e...  
WO/2021/041447A1
Systems and techniques to convert data value types. In at least one embodiment, data value types are converted by adjusting data floating point numbers to identify integer values and adjusting integer values to identify floating point nu...  
WO/2021/011320A1
Disclosed herein includes a system, a method, and a device for asymmetrical scaling factor support for negative and positive values. A device can include a circuit having a shift circuitry and multiply circuitry. The circuit can be confi...  
WO/2020/252769A1
Provided are a data storage method for a first input first output memory, and a device and a storage medium. A splicing unit, a random access storage unit and an output unit, which are connected in pairs, are configured for a first input...  
WO/2020/237114A1
A method for computing integral image values of an image in a hardware accelerator is provided that includes computing (2400) row sum values for each row of a row block of the image, wherein the row sum values for each row are computed i...  
WO/2020/236347A1
Systems, circuits, and methods for clock domain crossing for an interface between logic circuits are provided. A circuit is configured to allow an exchange of signals between a first logic circuit clocked using a first clock signal havin...  
WO/2020/222910A1
Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes a plurality of computing devices (or "tiles") coupled to a controller (e.g., and "orchestration contro...  
WO/2020/219621A1
A swatch presentation system is disclosed. The swatch presentation system may include a plurality of layers with an opening in a first layer. The first opening of the first layer allows for the viewing of a swatch. The swatch presentatio...  
WO/2020/214705A1
A method including, receiving a reply instruction issued by a user for a part of the content of any first message shown in a conversation window; receiving a reply content input by the user for the part of the content; in response to an ...  
WO/2020/197002A1
The present invention relates to a device for converting data inputted in a specific endian format into another endian format. A data conversion device according to one embodiment of the present invention comprises: a receiving unit for ...  
WO/2020/185896A1
The present disclosure provides methods for selectively tagging a subset of polynucleotide sequences from a plurality of polynucleotides comprising (a) synthesizing a plurality of polynucleotide sequences by flexible-write synthesis on a...  
WO/2020/181363A1
Provided are systems and methods to facilitate processing and communicating planning data for computer assisted surgery (CAS) procedures. Smart compression may be performed to reduce operational data (e.g. for encoding and/or communicati...  
WO/2020/177249A1
Disclosed is a virtual channel-based operation unit sharing system, comprising: multi-way component requesting ends, each way of the multi-way component requesting ends independently sending a request to an arbiter that has a certificate...  
WO/2020/176538A1
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite- sized hybrid analog-digital matrix processor ar...  
WO/2020/176448A1
In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/add...  
WO/2020/162899A1
A fluid ejection controller interface includes output logic to receive control data packets, each control data packet including a set of primitive data bits and a set of random bits. The fluid ejection controller interface includes count...  
WO/2020/160383A1
A distributed energy resource (DER) device is coupled to a utility meter in a "behind-the-meter" configuration. The utility meter analyzes a commitment generated by the DER device to determine a specific operation performed by the DER de...  
WO/2020/132277A1
An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The b...  
WO/2020/123055A1
Apparatus and methods are disclosed, including using a memory controller to generate an encoded physical address using a run length encoding (RLE) algorithm on a physical address to reduce a length of the encoded physical address, and st...  
WO/2020/118713A1
A bit width matching circuit, a data writing apparatus, a data reading apparatus, and an electronic device. The bit width matching circuit comprises: a cache array (101), a write control unit (102), and a read control unit (103). The cac...  

Matches 1 - 50 out of 7,034