Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 1 - 50 out of 9,373

Document Document Title
WO/2021/185262A1
A computing apparatus (402) for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing apparatus (402) may be comprised in a combined processing apparatus (40...  
WO/2021/141827A1
Embodiments of the disclosure provide method for performing contraction on a tensor network. The method can include: receiving, by a system, a tensor network comprising a plurality of tensors and a plurality of edges among the plurality ...  
WO/2021/134050A1
An electronic device includes a queue with multiple sub-queues arranged in a logical hierarchy from a lowest sub-queue to a highest sub-queue, each sub-queue including a separate subset of a set of entries of the queue, and a separate ag...  
WO/2021/105648A1
Data processing apparatuses, methods of data processing, complementary instructions and programs related to ring buffer administration are disclosed. An enqueuing operation performs an atomic compare-and-swap operation to store a first p...  
WO/2021/101451A1
Disclosed are a method and apparatus for storing data. The method includes: acquiring data to be stored; converting the data to be stored from an initial data type to a target data type, a data length corresponding to the target data typ...  
WO/2021/092352A1
Systems, methods, and computer program product embodiments are disclosed for removing any fixed frequency interfering signal from an input signal without introducing artifacts that are not part of the original signal of interest. An embo...  
WO/2021/081181A1
A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit ...  
WO/2021/067312A1
Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending ...  
WO/2021/050286A1
Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command (610) from a bus master coupled to the serial bus, determining that a sequence is being e...  
WO/2021/041447A1
Systems and techniques to convert data value types. In at least one embodiment, data value types are converted by adjusting data floating point numbers to identify integer values and adjusting integer values to identify floating point nu...  
WO/2021/011320A1
Disclosed herein includes a system, a method, and a device for asymmetrical scaling factor support for negative and positive values. A device can include a circuit having a shift circuitry and multiply circuitry. The circuit can be confi...  
WO/2020/252769A1
Provided are a data storage method for a first input first output memory, and a device and a storage medium. A splicing unit, a random access storage unit and an output unit, which are connected in pairs, are configured for a first input...  
WO/2020/237114A1
A method for computing integral image values of an image in a hardware accelerator is provided that includes computing (2400) row sum values for each row of a row block of the image, wherein the row sum values for each row are computed i...  
WO/2020/236347A1
Systems, circuits, and methods for clock domain crossing for an interface between logic circuits are provided. A circuit is configured to allow an exchange of signals between a first logic circuit clocked using a first clock signal havin...  
WO/2020/222910A1
Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes a plurality of computing devices (or "tiles") coupled to a controller (e.g., and "orchestration contro...  
WO/2020/219621A1
A swatch presentation system is disclosed. The swatch presentation system may include a plurality of layers with an opening in a first layer. The first opening of the first layer allows for the viewing of a swatch. The swatch presentatio...  
WO/2020/214705A1
A method including, receiving a reply instruction issued by a user for a part of the content of any first message shown in a conversation window; receiving a reply content input by the user for the part of the content; in response to an ...  
WO/2020/197002A1
The present invention relates to a device for converting data inputted in a specific endian format into another endian format. A data conversion device according to one embodiment of the present invention comprises: a receiving unit for ...  
WO/2020/185896A1
The present disclosure provides methods for selectively tagging a subset of polynucleotide sequences from a plurality of polynucleotides comprising (a) synthesizing a plurality of polynucleotide sequences by flexible-write synthesis on a...  
WO/2020/181363A1
Provided are systems and methods to facilitate processing and communicating planning data for computer assisted surgery (CAS) procedures. Smart compression may be performed to reduce operational data (e.g. for encoding and/or communicati...  
WO/2020/177249A1
Disclosed is a virtual channel-based operation unit sharing system, comprising: multi-way component requesting ends, each way of the multi-way component requesting ends independently sending a request to an arbiter that has a certificate...  
WO/2020/176538A1
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite- sized hybrid analog-digital matrix processor ar...  
WO/2020/176448A1
In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/add...  
WO/2020/162899A1
A fluid ejection controller interface includes output logic to receive control data packets, each control data packet including a set of primitive data bits and a set of random bits. The fluid ejection controller interface includes count...  
WO/2020/160383A1
A distributed energy resource (DER) device is coupled to a utility meter in a "behind-the-meter" configuration. The utility meter analyzes a commitment generated by the DER device to determine a specific operation performed by the DER de...  
WO/2020/132277A1
An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The b...  
WO/2020/123055A1
Apparatus and methods are disclosed, including using a memory controller to generate an encoded physical address using a run length encoding (RLE) algorithm on a physical address to reduce a length of the encoded physical address, and st...  
WO/2020/118713A1
A bit width matching circuit, a data writing apparatus, a data reading apparatus, and an electronic device. The bit width matching circuit comprises: a cache array (101), a write control unit (102), and a read control unit (103). The cac...  
WO/2020/117700A1
An IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second comma...  
WO/2020/081731A1
Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first d...  
WO/2020/069600A1
Methods and devices for encoding a point cloud. More than one frame of reference is identified and a transform defines the relative motion of a second frame of reference to a first frame of reference. The space is segmented into regions ...  
WO/2020/053622A1
Methods and systems for Long Term Evolution (LTE) and Fifth Generation (5G) beam index filtering are presented. According to one aspect, a method for beam index filtering comprises receiving a beam index that was estimated based on infor...  
WO/2020/010445A1
Methods and devices for lossy encoding of point clouds. Rate-distortion optimization is used in coding an occupancy pattern for a sub-volume to determine whether to invert any of the bits of the occupancy pattern. The assessment may be a...  
WO/2020/010444A1
Methods and devices for encoding a point cloud, where occupancy data for child sub-volumes is context-adaptively encoded based on contexts selected, at least in part, using an occupancy score determined for each child sub-volume. The occ...  
WO/2020/005602A1
Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A write operation can be executed by multiple write threads on a graphics processing unit (GPU) to write data to memory locations in ...  
WO/2019/232641A1
Systems and methods for automatic labeling of data with user validation and/or correction of the labels. In one implementation, unlabeled images are received at an execution module and changes are made to the unlabeled images based on th...  
WO/2019/210360A1
A method for use in colourising a three-dimensional (3D) point cloud of an environment, the method including determining timing information indicative of a time of capture of a frame; identifying at least some 3D points of the point clou...  
WO/2019/212664A1
A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes ...  
WO/2019/208566A1
In a processor device according to the present invention a memory access device reads processing subject data from an external memory, and writes the data to a first register group which, among a plurality of register groups, is not bein...  
WO/2019/199490A1
A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbit...  
WO/2019/183849A1
A data processing method and device. The method comprises: writing data in a first matrix into a register; carrying out a reading operation on the data of the first matrix in the register multiple times, wherein at least one piece of dat...  
WO/2019/166771A1
Control apparatus to control operation of a data buffer to which data items are written according to a write pointer which advances in position in response to an input data item rate and from which data items are read according to a read...  
WO/2019/144112A1
Methods for harmonization of test results from a biological sample in a multiplexed biochemical assay, wherein presence and/or concentration of multiple biomarkers are determined at the same time in the same sample, making test results o...  
WO/2019/136094A1
A system and method for adapting an audios stream for reducing latency. The method may include the steps of, and the system may function to, receive an audio stream having a packet buffer and an audio buffer, measure the audio buffer dep...  
WO/2019/126869A1
A system for operating a configuration platform. The system comprising a conversion pipeline, the conversion pipeline allowing converting a first set of data associated with a computer-aided design (CAD) system into polygon meshes suitab...  
WO/2019/125265A1
The invention solves the problems of delay between signals intended for parallel / simultaneous reproduction, between a certain point until the signals have been sampled and have got a common clock domain. The delays are caused, for exam...  
WO/2019/117854A1
The examples include methods and apparatuses to store events in a queue for an EC, Storing events in a queue for an EC can include receiving a message from a core FW of an EC and identifying an event corresponding to the message. Storing...  
WO/2019/113628A1
Embodiments of the invention relate to methods and systems for processing a network data block. One or more embodiments of the invention include receiving network data at a receiver/transmitter comprising a serializer/deserializer (SERDE...  
WO/2019/101350A1
A data bus comprises process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages comprising a buffer element configured to buffer a data bit s...  
WO/2019/075504A1
Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge ...  

Matches 1 - 50 out of 9,373