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WO/2023/133997A9 |
A method for preparing a semiconductor device, and a semiconductor device. The preparation method comprises: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region; forming a first ...
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WO/2023/184421A9 |
A thin film transistor, a display substrate and a display apparatus. The thin film transistor comprises: a gate electrode (20), which is arranged on a base substrate (10); an active layer (30), which is located between the gate electrode...
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WO/2023/228473A1 |
This silicon carbide semiconductor device is provided with a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein: the silicon carbide substrate has a drift region ha...
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WO/2023/225831A1 |
The present disclosure relates to the technical field of semiconductors, and provides a nanowire, an array substrate preparation method, an array substrate, and an electronic device, capable of solving the problem that the area of an act...
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WO/2023/227992A1 |
The present invention provides a semiconductor device that achieves both low power consumption and high performance. Provided is a semiconductor device comprising a first semiconductor layer, a second semiconductor layer, a first conduct...
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WO/2023/228899A1 |
This nitride semiconductor device (10) comprises: a substrate (12); an electron transit layer (16) that is disposed above the substrate (12) and which has a side wall surface (16E) exposed above the substrate (12); an electron supply lay...
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WO/2023/228605A1 |
This laminate structure (100) comprises a buffer layer (106), a first semiconductor layer (108), and a second semiconductor layer (110). The buffer layer and the first semiconductor layer overlap one another in a vertical direction. The ...
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WO/2023/228389A1 |
A magnetoresistive effect element according to the present invention is provided with a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer. The nonmagnetic layer is positioned between the first ferromagnetic...
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WO/2023/221110A1 |
The present disclosure relates to the technical field of semiconductors, provides a nanowire, a thin film transistor preparation method, a thin film transistor, and a semiconductor device, and can solve the problem of nanowires. A nanowi...
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WO/2023/223657A1 |
This method for manufacturing semiconductor device includes: forming an oxide semiconductor layer on a substrate through the sputtering method; placing the substrate having the oxide semiconductor layer formed thereon in a heating furnac...
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WO/2023/223127A1 |
A semiconductor device having a high storage density is applied in the present invention. This semiconductor device has a first layer and a first insulating material. The first layer has a first oxide semiconductor, first to ninth conduc...
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WO/2023/224113A1 |
This semiconductor device comprises: a first switching element; a first primary connection member; and a first secondary connection member. The first switching element includes a first electrode which is disposed on a first side in the t...
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WO/2023/223588A1 |
A semiconductor chip (1) comprises a plurality of transistor cells (100) arranged side by side in a first direction (Y), wherein the transistor cells extend in a second direction (X) perpendicular to the first direction and have first-co...
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WO/2023/223858A1 |
Provided is a gallium nitride semiconductor device comprising: an amorphous glass substrate; a gallium nitride semiconductor layer on a first surface of the amorphous glass substrate; and a compensation layer on a second surface of the a...
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WO/2023/220962A1 |
The present application provides a ferroelectric field effect transistor, a ferroelectric random-access memory, and a manufacturing method. The ferroelectric field effect transistor comprises a silicon-based substrate, a semiconductor la...
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WO/2023/224603A1 |
Semiconductor devices and methods, including metal oxide silicon field effect transistor (MOSFET) devices and methods. The semiconductor device, such as a MOSFET, includes two source regions; a drain region; two body regions, and a buffe...
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WO/2023/223499A1 |
A semiconductor device (10) according to the present invention is a field-effect transistor comprising a gate electrode (110) located between a source electrode (108) and a drain electrode (109), a carrier traveling between the source el...
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WO/2023/223589A1 |
A semiconductor chip (1) is provided with a plurality of transistor cells (100) disposed side-by-side along a first direction (Y), wherein the transistor cells comprise gate wires (22a, 22b) extending along a second direction (X) orthogo...
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WO/2023/221552A1 |
The present application relates to the technical field of semiconductors, and provides a Schottky transistor, a diode, and a cold source semiconductor structure and a preparation method therefor. The cold source semiconductor structure c...
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WO/2023/223328A1 |
A semiconductor transistor comprising: a drain region; a plurality of source regions; and a plurality of gate regions interleaved with the source regions.
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WO/2023/224062A1 |
This energy conversion element has a ferromagnetic region. The ferromagnetic region receives an elastic wave that advances in a first direction, and generates, in a second direction which intersects the first direction, a direct current ...
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WO/2023/221354A1 |
A memory, a dynamic random access memory, and an electronic device. The memory may be a 3D memory, and comprises: a substrate; and a plurality of storage unit columns distributed in a first direction perpendicular to the substrate, where...
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WO/2023/221351A1 |
Embodiments of the present application provide a gallium nitride HEMT device, comprising: a silicon substrate; a gallium nitride base layer located on the silicon substrate; an HEMT device formed on the gallium nitride base layer and com...
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WO/2023/223722A1 |
The present invention improves the mutual conductance (gm) of a field effect transistor. A semiconductor device according to the present invention is provided with: an island-like semiconductor unit which has an upper surface part and a ...
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WO/2023/223936A1 |
[Problem] The present invention addresses the problem of providing a silicon nitride etching liquid composition which, for production of 3D non-volatile memory cells, or the like, is capable of suppressing the regrowth of silicon oxide i...
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WO/2023/223590A1 |
A semiconductor chip (1) comprises a plurality of transistor cells (100) arranged side by side in a first direction (Y). Each transistor cell has a gate wire (22a, 22b) that extends in a second direction (X) that is orthogonal to the fir...
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WO/2023/224792A1 |
A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel lay...
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WO/2023/223126A1 |
Provided is a semiconductor device having a novel configuration. The present invention has: a base die having a first power supply circuit that generates a first voltage; a first die having a second power supply circuit that generates a ...
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WO/2023/224059A1 |
Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided in contact with the upper surface of the semicond...
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WO/2023/224332A1 |
Provided is a tunneling field-effect transistor. The tunneling field-effect transistor is defined by an element isolation film disposed on a substrate, and includes a semiconductor pattern that has a protruding pin-like shape protruding ...
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WO/2023/223337A1 |
Disclosed are an improved PMMA gate dielectric based and miniaturized bottom-gate bottom-contact type (BG-BC) organic thin film transistor as shown in FIG. 2 and a method of manufacturing the same. The present invention comprises a prist...
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WO/2023/224942A1 |
A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a thir...
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WO/2023/224331A1 |
A tunneling field effect transistor is provided. The tunneling field effect transistor is defined by a device isolation layer disposed on a substrate, and comprises a fin-shaped semiconductor pattern that protrudes farther upward than an...
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WO/2023/224092A1 |
This nitride semiconductor device is provided with: a semiconductor substrate; a transistor which is configured from a nitride semiconductor that is formed on the semiconductor substrate, while comprising a drain electrode, a source elec...
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WO/2023/224996A1 |
A method of processing a substrate that includes: loading the substrate in a plasma processing chamber, the substrate having a surface including an oxide, the oxide including an alkaline earth metal; flowing a process gas including CCl4 ...
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WO/2023/223375A1 |
According to the present invention, an oxide layer (102) which is configured from an oxide that does not contain Si is formed on a substrate (101). Subsequently, a bonding layer (103) which is configured from AlN is formed on the oxide l...
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WO/2023/224351A1 |
The present invention relates to a transistor and to a method for manufacturing same and, more specifically, to a transistor having improved characteristics and to a method for manufacturing same. A transistor, according to an embodiment...
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WO/2023/220872A1 |
A nitride-based semiconductor integrated circuit (IC) chip (100) including at least one transistor (Q) and a temperature sensor (T) configured for sensing temperature of the transistor (Q). The transistor (Q) and the temperature sensor (...
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WO/2023/224790A1 |
An electronic device includes a two-dimensional electron system (2DES) having a two-dimensional electron gas (2DEG) area, and a plurality of contacts arranged around the 2DEG area. Charge particle transport is confined within the 2DEG ar...
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WO/2023/216309A1 |
An electronic apparatus, comprising a first metal layer (30) and a second metal layer (40). The first metal layer (30) and the second metal layer (40) are arranged in different layers; the first metal layer (30) comprises a plurality of ...
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WO/2023/216648A1 |
The present invention provides a method for improving epitaxial growth stability of a super-junction structure and preparing a semiconductor device. A second conductive type doped column of the super-junction structure is formed by combi...
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WO/2023/218279A1 |
Provided is a semiconductor device that has a high storage density and is highly reliable. The semiconductor device comprises first to third layers that are laminated. The first layer includes a delay signal generation circuit and a row ...
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WO/2023/216167A1 |
A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based semiconductor layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate ...
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WO/2023/219792A1 |
A vertical semiconductor and method for fabricating the same is disclosed. In one embodiment, fabrication entails providing a precursor comprising a substrate and a drift region over the substrate. A plurality of trenches is etched into ...
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WO/2023/216884A1 |
A three-dimensional memory device having vertical transistors and a method for forming the same are disclosed. In an example, the memory device includes an array of memory cells each including a vertical transistor. Along a first directi...
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WO/2023/219570A1 |
Various embodiments may provide a transistor. The transistor may include a substrate, a first contact electrode and a second contact electrode over the substrate. The transistor may additionally include a two-dimensional semiconductor ma...
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WO/2023/216693A1 |
The present invention relates to the technical field of semiconductors. Disclosed are a three-dimensional integrated circuit and a manufacturing method therefor, used for improving the performance of the integrated circuit when the integ...
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WO/2023/220104A1 |
A logic power network provided in an application-specific integrated circuit (ASIC). The ASIC includes a central processor. The ASIC also includes at least one intellectual property (IP) core operatively connected with the central proces...
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WO/2023/220001A1 |
Disclosed herein is a method for fabricating a nanowire array on an uneven or curved surface. A pliable, porous scaffold is used to hold a liquid electrolyte, creating s semi-solid electrolyte that is used to transfer pressure to a templ...
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WO/2023/219135A1 |
A power conversion device according to the present invention converts power using a semiconductor device, and is characterized by comprising: a MOS control diode 1 that has an n+ layer 11, an n- layer 12, a p- layer 13, a p+ layer 14, a ...
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