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WO/2023/184613A1 |
Provided in the present invention are an array substrate and a manufacturing method therefor. The manufacturing method for an array substrate comprises: using a first photomask to form a light-shielding layer, a source electrode and a dr...
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WO/2023/189870A1 |
A sputtering target comprising an oxide sintered body containing indium oxide as the main component, wherein the oxide sintered body has a contained hydrogen concentration of 5×1016 atoms/cm3 or greater, the atomic concentration ratio (...
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WO/2023/188653A1 |
An acceleration sensor according to the present invention comprises: a device-side substrate that has a first main surface and a second main surface opposite of the first main surface; a recess that is indented from the first main surfac...
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WO/2023/188755A1 |
This semiconductor device (10) comprises: a semiconductor layer (12) including a first surface (12A) and a second surface (12B) on the opposite side from the first surface (12A); a source trench (22) formed on the semiconductor layer (12...
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WO/2023/185195A1 |
The present application relates to the technical field of semiconductors, and particularly relates to a Schottky diode and a power circuit. The Schottky diode comprises: a first layer; a second layer, which is in contact with the first l...
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WO/2023/189438A1 |
This semiconductor device includes: a chip having a main surface; a trench insulation structure formed on the main surface of the chip; a first conductivity-type body region formed on a surface layer section of the main surface so as to ...
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WO/2023/189487A1 |
This semiconductor device comprises: a metal oxide layer on an insulating surface; an oxide semiconductor layer on the metal oxide layer; and an insulating layer on the oxide semiconductor layer. The insulating layer includes a first reg...
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WO/2023/189491A1 |
This semiconductor device includes: a metal oxide layer which is above an insulating surface; and an oxide semiconductor layer which is above the metal oxide layer. The fluorine concentration of the metal oxide layer is at least 1 × 101...
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WO/2023/186995A1 |
The present invention relates to a logic device (10) comprising: - a first and a second arm (12) through which a charging current passes; - a channel (16) that connects the arms (12, 14) and comprises a first zone of contact with the fir...
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WO/2023/188970A1 |
A semiconductor device (1) for power amplification comprises: a substrate (10); a lower surface electrode (64); a semiconductor layer (20); a source electrode (60); a drain electrode (50); a gate electrode (40); a gate finger (42); and a...
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WO/2023/191445A1 |
The present invention relates to a three-dimensional stacked DRAM array and a manufacturing method therefor, wherein, by vertically stacking a "U"-shaped drain-BL connection structure having two connection lines, a plurality of horizonta...
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WO/2023/188560A1 |
The present invention provides a semiconductor device, a method for manufacturing a semiconductor device, and an electric power converter, which make it possible to prevent an increase in an on-voltage of an IGBT, and to improve the reve...
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WO/2023/191489A1 |
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In one embodiment, a method for manufacturing a semiconductor device may comprise the steps of: growing a stack layer by alter...
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WO/2023/185712A1 |
Provided in the embodiments of the present invention are a power semiconductor device, and a related circuit, a chip, an electronic device and a preparation method. The semiconductor device optimizes the front-surface structure of a diod...
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WO/2023/189550A1 |
A semiconductor device (10) according to the present invention comprises an oxide semiconductor layer (140) that is provided on an insulation surface, a gate insulating layer (150) that is provided on the oxide semiconductor layer, and a...
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WO/2023/191776A1 |
An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to ...
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WO/2023/188756A1 |
A semiconductor device (10) comprises: a semiconductor layer (12); a trench (20) that is formed in the semiconductor layer (12) and includes a side wall (20A); an insulation layer (14) formed on the semiconductor layer (12), and a gate e...
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WO/2023/189053A1 |
The semiconductor device includes: a chip having a major surface; a trench resistive structure formed on the major surface; a gate pad having a lower resistance value than the trench resistive structure and disposed over the trench resis...
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WO/2023/184600A1 |
Provided in the present application are an array substrate and a preparation method therefor, and a display panel. An active region of a base substrate is coated with a first ink to form an active-layer pattern, and a channel region of t...
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WO/2023/188561A1 |
Provided are a semiconductor device and a power conversion device capable of improving recovery characteristics by reducing the area of a p-body layer of a diode part of an RC-IGBT to suppress hole injection. A semiconductor device 100...
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WO/2023/189164A1 |
This semiconductor device comprises an insulating film covering an electrode and a base surface of a semiconductor substrate. The insulating film has a first upper surface and a protrusion protruding from the first upper surface, respect...
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WO/2023/183987A1 |
The present invention broadly relates to the fabrication and processing of graphene electronic devices on silicon which comprise a silicon dioxide passivation layer.
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WO/2023/192693A1 |
Described herein is an apparatus and a method for thermal management. The apparatus includes an integrated circuit (IC) including at least one field effect transistor, wherein each at least one FET comprises a gate, a drain, and a source...
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WO/2023/184236A1 |
Provided in the present disclosure are a metal oxide thin film transistor, an array substrate and a display apparatus, which belong to the technical field of display, and can solve the problem of poor stability of existing metal oxide th...
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WO/2023/189052A1 |
This semiconductor module includes an IGBT device and a MISFET device that constitutes a parallel circuit with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range lower than the bui...
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WO/2023/188577A1 |
Provided are a semiconductor device and a power conversion device with which the p-body layer area of a diode portion of an RC-IGBT can be reduced, hole injection can be suppressed, and the recovery characteristic can be improved. This...
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WO/2023/184351A1 |
Embodiments of the present disclosure provide a metal oxide thin film transistor. The metal oxide thin film transistor comprises a metal oxide semiconductor layer (102) arranged on a base substrate (101), and a source electrode (103) and...
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WO/2023/188867A1 |
This semiconductor device comprises: a chip having a main surface; a pn joint that extends in the horizontal direction along the main surface inside the chip; a trench insulation structure that is formed on the main surface so as to pene...
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WO/2023/188818A1 |
The present invention provides a vibration element having a structure which can efficiently convert an electric field into a magnetic field or vice versa. The vibration element according to the present technology comprises a vibration ...
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WO/2023/191435A1 |
Disclosed are a power semiconductor device having reduced loss, and a method for manufacturing same. The power semiconductor device comprises: a first drift region of a first conductivity type; a second drift region of the first conducti...
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WO/2023/189493A1 |
This semiconductor device that can realize a highly reliable high-mobility semiconductor device, comprises: a metal oxide layer disposed on a substrate and having aluminum as a main component; an oxide semiconductor layer disposed on the...
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WO/2023/184914A1 |
Provided in the embodiments of the present application are an MOS transistor, a memory and a manufacturing method therefor. In the MOS transistor provided by the embodiments of the present application, a source structure, a metal oxide s...
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WO/2023/184587A1 |
Disclosed in the present application are an array substrate and a display panel. The array substrate comprises a substrate, a gate electrode, a gate insulating layer, an oxide semiconductor layer and a source/drain metal layer, wherein a...
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WO/2023/189489A1 |
This semiconductor device includes a substrate, an insulating layer over the substrate, a metal oxide layer over the insulating layer, and an oxide semiconductor layer over the metal oxide layer. The insulating layer includes a first reg...
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WO/2023/189004A1 |
This oxide semiconductor film has crystalline properties and is provided on a substrate, the oxide semiconductor film including an indium (In) element, and a first metal (M1) element selected from the group consisting of an aluminum (Al)...
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WO/2023/189057A1 |
A semiconductor device (1A) comprises: a chip (2) that comprises a SiC single crystal and has a major surface (3); a trench structure (20) that includes a first sidewall (22A) extending in an a-axis direction of the SiC single crystal an...
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WO/2023/184129A1 |
A semiconductor device includes a first and a second nitride-based semiconductor layers and a gate structure. The gate structure includes an outer spacer, an inner spacer and a gate electrode. The outer spacer has at least two opposite i...
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WO/2023/189059A1 |
This semiconductor device includes: a chip having a first main surface on one side and a second main surface on another side; an IGBT region provided to an inner portion of the first main surface; an outer peripheral region provided to a...
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WO/2023/189161A1 |
This semiconductor device comprises: a chip having a main surface; a trench that demarks a first region on one side and a second region on the other side in the chip in a cross-sectional view; a plurality of trench insulating structures ...
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WO/2023/184812A1 |
Disclosed in the present invention are a heterojunction-based high-power-density tunneling semiconductor device and a manufacturing process therefor. A cell structure of the device comprises: an N+ substrate, wherein a drain metal is arr...
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WO/2023/188971A1 |
A semiconductor device (1) for power amplification comprises: a substrate (10); a lower surface electrode (64); a semiconductor layer (20); a source electrode (60); a drain electrode (50); a gate electrode (40); and a field plate (80). T...
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WO/2023/184622A1 |
A display panel and a display apparatus. The display panel comprises a substrate (10) and a thin film transistor layer (20) arranged on the substrate (10). The thin film transistor layer (20) comprises an active layer (21) and a metal la...
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WO/2023/184571A1 |
The present invention relates to a semiconductor structure and a preparation method therefor. The preparation method for the semiconductor structure comprises: providing a substrate, the substrate comprising an array region and a periphe...
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WO/2023/189048A1 |
This nitride semiconductor device comprises: an electron transit layer; an electron supply layer that is formed on the electron transit layer and that has a band gap which is larger than that of the electron transit layer; a dielectric l...
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WO/2023/189054A1 |
A semiconductor device including: a chip having a major surface; a gate resistor including a trench resistive structure formed on the major surface; a gate pad having a lower resistance value than the trench resistive structure and dispo...
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WO/2023/184927A1 |
Provided in the embodiments of the present application are a field-effect transistor, a memory and a preparation method therefor, a semiconductor array, and a transistor. The field-effect transistor comprises a stacked structure and two ...
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WO/2023/189060A1 |
This SiC semiconductor device (1A) contains: a chip (2) which contains an SiC monocrystal and has a main surface (3); a trench structure (20) which has side walls (21, 22) and a bottom wall (23) and is formed in the main surface; and a f...
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WO/2023/189505A1 |
A semiconductor device (1) includes: a chip (9) having a main surface (10); a trench insulating structure (17) formed in the main surface; a gate insulating film (28) covering the main surface so as to connect to the trench insulating st...
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WO/2023/189506A1 |
This semiconductor device includes: a semiconductor chip that has a first main surface and a second main surface which is on the opposite side of the first main surface; an insulating gate-type first transistor which is formed on the sem...
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WO/2023/189549A1 |
In this method for producing a semiconductor device, a metal oxide layer mainly composed of aluminum is formed on an insulating surface, the surface of the metal oxide layer is subjected to planarization, an oxide semiconductor layer is ...
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