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JPH0325358Y2 |
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JPH0335855B2 |
PURPOSE:To realize a flip-flop circuit which has a function of an inverter in addition to its normal working, by using a control circuit which always sets a circuit of one side under an open state regardless of an input signal. CONSTITUT...
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JPH03124121A |
PURPOSE: To simplify the design and to decrease the number of networks by advancing stepwise an input clock to make inputs to a NAND circuit all to logical '1', making outputs from the NAND circuit logical '0', resetting a D flip-flop(FF...
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JPH03121620A |
PURPOSE: To attain high speed operation by tying the output terminals of a couple of load resistors with a high value resistor to operate the FET of a differential amplifier in switching operation at the saturation region. CONSTITUTION: ...
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JPH03117023A |
PURPOSE: To always obtain a stable operation property without being affected by a change, etc., in the threshold voltage of an FET due to fluctuation of a wafer process by constituting a circuit to supply bias to a transfer gate the same...
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JPH0332246B2 |
An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subseque...
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JPH03109817A |
PURPOSE: To enhance the degree of freedom for setting a switching pattern of a swallow counter by adopting the circuit constitution comprising the swallow counter, a shift register and a multiplexer so as to apply an integral division of...
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JPH0331015B2 |
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JPH03106223A |
PURPOSE: To prevent a pulse width of a carrier signal from being made thin even when multi-stages of n-bit binary counters are connected in cascade hy providing plural flip-flops and a k-bit shift register and outputting a clock signal i...
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JPH03106124A |
PURPOSE: To frequency-divide an input signal into an output signal of 1/3 frequency by using the OR signal of outputs of 2nd and 3rd AND gates as its clock input, using its own inverted output as its input and outputting an output signal...
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JPH03101312A |
PURPOSE: To reduce the variation of a delay time from operating a start signal to outputting by automatically resetting all flip flops when power is supplied and giving the operation start signal to only one flip flop. CONSTITUTION: The ...
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JPH0344931U |
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JPH0388422A |
PURPOSE: To improve operating speed by dividing a bit number of a synchronizing counter into two by 1st and 2nd synchronizing counter circuits, and adjusting the timing of the output of each synchronizing counter with plural flip-flops. ...
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JPH0326929B2 |
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JPH0385920A |
PURPOSE: To frequency-divide a clock signal at a high frequency at a high speed by outputting a signal whose level is changed from a signal conversion circuit in the inside of a signal output stage and supplying the signal to an expansio...
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JPH0382221A |
PURPOSE: To make the relation of phase of two frequency division outputs stable by forming a frequency divider circuit with one flip-flop and one delay element in place of provision of the frequency divider circuit with two flip-flops. C...
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JPH0378249A |
PURPOSE: To increase the mounting density of a printed board by disposing into a given shape a terminal connected with a chip by bonding, and inputting data into the chip by switch operation. CONSTITUTION: An input/output terminal 2, a c...
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JPH0322104B2 |
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JPH0369212A |
PURPOSE: To realize a counter programmed even at the time of resetting, and to prevent a peripheral circuit from being enlarged as well by providing a write enable detection circuit which detects a write enable signal and supplies the ou...
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JPH0311954Y2 |
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JPH0327128U |
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JPH0362616A |
PURPOSE: To set a required frequency division value even when it is other than an integer number by providing an inverting circuit, a changeover circuit and a variable split counter circuit or the like, switching the changeover circuit w...
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JPH0319727B2 |
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JPH03501196A |
An N stage Gray code generator includes an N stage binary counter having an input for receiving clock pulses to be counted and providing N outputs forming an N bit binary code. N minus 1 storage stages capable of being toggled between a ...
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JPH0357320A |
PURPOSE: To set a frequency division value freely as an integral number by providing a DC/DC converter circuit or the like comprising a switching element, a smoothing circuit section, a comparator and a reference voltage circuit section ...
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JPH0322435U |
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JPH0316805B2 |
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JPH0346411A |
PURPOSE: To attain normal counting without being affected by a bit length of a counter or the frequency of a clock pulse by providing a circuit generating a carry signal in timewise proceeding over a counting operation timing. CONSTITUTI...
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JPH0341824A |
PURPOSE: To easily set an optional frequency division value without provision of an external circuit by providing n-stage of counter circuits receiving a reference clock pulse, and counting the pulse in binary, an OR circuit, n-set of sw...
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JPH0341823A |
PURPOSE: To divide a frequency into 1/(2n-1) of a frequency of an original signal and to output a waveform whose duty factor is 50% by providing plural shift registers or the like to attain the operation without the effect of the transit...
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JPH0312805B2 |
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JPH0312804B2 |
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JPH0311691B2 |
PURPOSE:To operate a counter circuit at plural counting speeds by feeding back the counter output of final stage to a counter of the middle stage and allowing the counter of the middle stage to count a clock counted by the initial stage....
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JPH0311689B2 |
After detecting a leading edge of a stop control signal (STBY) supplied from an external circuit, an oscillation output signal (OSC) is cut off at an input side of a frequency divider (24) in synchronism with the first leading edge of a ...
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JPH035921Y2 |
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JPH0311125B2 |
PURPOSE:To execute easily the counter test, by adding a simple input circuit to a D-type flip-flop (DFF) circuit to give the scanning function to it. CONSTITUTION:An inverter I3 and an input gate G3 are provided in parallel with an inver...
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JPH0314834U |
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JPH0329515A |
PURPOSE: To generate plural kinds of rectangular wave signals whose frequencies are close to each other without increasing a system clock frequency especially by inverting a clock signal to a counter for each reset of the counter, and ou...
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JPH038124B2 |
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JPH038128B2 |
A high frequency divider arrangement for use in transmission systems operating in the gigabit/second range. Known divider arrangements based on ECL logic families have an upper frequency limit which is too low for dividing signals in the...
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JPH0316317A |
PURPOSE: To simplify the operation by applying (R-1) frequency division to an I/D(Increment/Decrement) clock of an Rf0 in case adding one pulse, and applying (R+1) frequency division to the I/D(Increment/Decrement) clock of the Rf0 in ca...
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JPH0316429A |
PURPOSE: To quickly and completely inspect an M-bit binary counter including carry propagation also by decoupling respective stages of the M-bit binary counter including plural stages, and after independently checking respective stages, ...
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JPH0313122A |
PURPOSE: To constitute a frequency dividing circuit equipped with reset function not to lower speed for (operation by monitoring the output of each partial circuit and stopping the operation of the frequency dividing circuit in a precedi...
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JPH033851U |
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JPH032743U |
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JPH03758Y2 |
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JPH034618A |
PURPOSE: To execute optionally even and odd number frequency division by one clock frequency dividing circuit by feeding back an output clock of a 1/2 frequency divider to other input terminal of an exclusive OR gate at odd number freque...
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JPH03811B2 |
synchronous binary circuit comprising a counter including J-K flip-flops (FF1 to FF8) constituting lower ! bit stages and higher m bit stages, first logic means (1, 2;13 to 16) for feeding, to J and K input terminals of each of flip-flop...
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JPH03812B2 |
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JPH03813B2 |
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