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JPH04192624A |
PURPOSE: To check a fault of a logic gate by forming a test circuit able to check a fault of a logic gate for adjusting number of simultaneous change and for load capacitance adjustment. CONSTITUTION: J-K flip-flops 1-6 consisting of the...
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JPH0440894B2 |
A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge trans...
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JPH04186924A |
PURPOSE: To offer a counter circuit for realizing a counting operation executed at a high speed and surely by allowing it to execute, in parallel the operations of an increment and a decrement while preceding an increment or decrement in...
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JPH0439691B2 |
A data processor having an integral timer including a clock generator producing a specific frequency output comprises a counter chain having an input and output thereof for supplying a fixed frequency divide function. A programmable pres...
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JPH0439690B2 |
A programmable high resolution timing system includes a selectable modulus prescaler counter (16). In one embodiment a high frequency clock (14) is coupled to a prescaler counter (16) which provides an output signal (TA/TM) every predete...
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JPH0426884Y2 |
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JPH04178024A |
PURPOSE: To improve operating frequency by devising the PLL circuit such that a pulse width of a preset signal generated by a preset signal generating circuit is expanded. CONSTITUTION: A prescaler 7 having two frequency divider ratios a...
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JPH0438166B2 |
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JPH04175012A |
PURPOSE: To realize an integrated counter circuit with a small size and minimum number of components by inserting an RS latch circuit between a pulse generating circuit and a ripple up-counter in an up-counter circuit. CONSTITUTION: When...
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JPH04172717A |
PURPOSE: To transmit a signal without hazard as an output of a final stage by inputting an external input signal to a 1st counter means in flip-flop operation and sending an output resulting from shifting a tail edge of an input signal f...
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JPH04172018A |
PURPOSE: To operate even by a high speed clock by inputting a counter pulse signal synchronously with the clock of the precharge signal of a carry generating circuit. CONSTITUTION: This circuit is equipped with latch circuits 1 and 3 for...
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JPH04172822A |
PURPOSE: To enable an up-down counter to make up- and down-counting at an arbitrary pitch by connecting the outputs of latch circuits to the inputs of full adders and, at the same time, the outputs of the full adders to the inputs of the...
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JPH04170818A |
PURPOSE: To prevent a frequency-divided clock from being delayed behind an original clock even if the number of frequency-dividing stages is increased by setting an output signal to a first or a second level by the frequency-divided outp...
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JPH04165817A |
PURPOSE: To vary and adjust a frequency dividing operation frequency range by connecting one end of a Schottky diode to each source of first and second switches FET, and supplying a reverse bias voltage from the other end. CONSTITUTION: ...
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JPH0434326B2 |
PURPOSE:To obtain a dynamic frequency divider capable of deviding to broad band areas while withstanding power supply fluctuation by adopting a double loop constitution in which a differential amplifier is employed in place of an inverte...
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JPH04503135A |
A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which ...
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JPH0432572B2 |
PURPOSE:To simplify constitution and to reduce chip size, by providing complementary constitution for only one input and using the constitution of an MOSFET and a load element for other inputs. CONSTITUTION:When all inputs a0-a3 are at a...
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JPH04156720A |
PURPOSE: To adapt the device to various kinds of loads connected to an output circuit by constituting a pulse conversion circuit of an output pulse signal setting part, a subtraction counter an AND gate, and an addition counter. CONSTITU...
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JPH0431325B2 |
A microprocessor is utilized to store a total accumulated driven mileage (odometer) signal in a non-volatile random access memory (RAM). Trip mileage manual pushbuttons are coupled to the microprocessor and enable the calculation and dis...
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JPH04151912A |
PURPOSE: To suppress a rising time or falling time delay of a frequency division output with respect to an input clock signal by driving a level setting section based on a control signal and an output of a delay section at the rise and f...
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JPH04150226A |
PURPOSE: To attain the miniaturization of a circuit by giving either of an H level and an L level to a programmable divider as a frequency division ratio setting signal when the level of plural input terminals used for setting the freque...
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JPH04150413A |
PURPOSE: To prevent the mulfunction of this circuit used for a logic circuit by providing a spike removing circuit composed of m-stage delay flip flops, an AND gate, and a set/reset flip flop in the title circuit. CONSTITUTION: When a re...
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JPH04145721A |
PURPOSE: To detect a malfunction by itself by providing plural FFs, plural parallel transistors(TRs) switched by the output of the FFs and resistive elements connected in series to the device. CONSTITUTION: When the circuit is normally i...
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JPH0429249B2 |
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JPH04142116A |
PURPOSE: To heighten the upper limit of an operable input frequency by enabling the output terminal of each data latch flip-flop to be connected to only one input. CONSTITUTION: The true signal output terminal Q1 and the auxiliary signal...
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JPH04140921A |
PURPOSE: To realize this counter circuit with a few circuit components by using a single counter so as to realize a counter function for plural counters to suppress the dispersion in a delay time. CONSTITUTION: Count of a counter circuit...
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JPH0455831U |
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JPH04137820A |
PURPOSE: To realize a frequency division circuit capable of a prescribed operation even when the electric characteristics of a transfer gate and an inverter circuit are changed by providing a bias compensation circuit on this circuit. CO...
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JPH04129329A |
PURPOSE: To simplify the circuit constitution, to attain the effect of reduction in number of elements and to attain especially the effect in the case of realizing a high-degree counter by activating a high-order bit with an up-carry or ...
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JPH04127718A |
PURPOSE: To easily recognize an error state by deciding a count clock and a count direction according to an inputted pulse signal, and inhibiting the transmission of the count clock according to an abnormality detection signal when any o...
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JPH0424891B2 |
A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) ...
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JPH0423965B2 |
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JPH0446725U |
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JPH04117727A |
PURPOSE: To prevent the malfunction of this counter circuit by providing 2-stages of delay flip-flops generating a pulse to load an n-bit counter to the counter circuit so as to make the holding time of the counter sufficient. CONSTITUTI...
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JPH04115623A |
PURPOSE: To realize a frequency divider circuit having large frequency dividing ratio by a small-scale circuit by combining and decoding the outputs of plural ring counters having frequency dividing ratios in prime relation to each other...
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JPH04107009A |
PURPOSE: To obtain a frequency divided pulse of high frequency precision by constituting a programmable counter for minute frequency change of at least two programmable counters. CONSTITUTION: A programmable counter SC for minute frequen...
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JPH0439740U |
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JPH04101514A |
PURPOSE: To enhance the processing speed of an absolute-value binary up/down counter by adding a means of inversing an up/down signal to the binary up/ down counter when counting a negative number. CONSTITUTION: When the output from outp...
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JPH04100319A |
PURPOSE: To count a large number with less carry propagation stage number by employing a counter able to count divisors A, B,* of a number having a large number N as a least common multiple so as to count the number Y. CONSTITUTION: A 1-...
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JPH0420286B2 |
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JPH0420126B2 |
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JPH0438137U |
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JPH0417488B2 |
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JPH0494216A |
PURPOSE: To obtain a signal whose duty ratio is 50% resulting from odd number frequency division of an input pulse signal by changing a level of an output signal as L, H, L,... at every an N (odd number)/2 period of the input pulse signa...
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JPH0417489B2 |
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JPH0416968B2 |
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JPH0490227A |
PURPOSE: To surely detect synchronization of a multi-frame signal by detecting respectively a horizontal synchronizing signal and a vertical synchronizing signal of a frame adjustment signal. CONSTITUTION: One multi-frame MFL consists of...
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JPH0487415A |
PURPOSE: To vary the output timing of the frequency dividing circuit to an input clock by providing a first and a second switches for inputting outputs of a first latch circuit and a second latch circuit, respectively, and switching each...
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JPH0483425A |
PURPOSE: To immediately generate pulses having a specified period by comparing current pulse period setting information with the preceding pulse period setting information and at the time of detecting a change, loading the new pulse peri...
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JPH0481123A |
PURPOSE: To allow the circuit to be hardly affected by power fluctuation by providing an initial value generating circuit and using an initial value designation signal so as to set an initial value of a 1/n frequency divider circuit and ...
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