| Document |
Document Title |
|
JPH03261223A |
PURPOSE: To prevent malfunction of a frequency synthesizer by providing a phase inversion circuit able to invert a phase of an output of a variable frequency divider circuit with a control signal to the output of the variable frequency d...
|
|
JPH0373176B2 |
A clock generator circuit of this invention is for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock. Three flip-flops, two of which are connected in series, and two logical gates ...
|
|
JPH0373178B2 |
|
|
JPH03261222A |
PURPOSE: To prevent occurrence of malfunction of a frequency synthesizer by providing a logic inverter between an output of a variable frequency divider circuit and an input of a frequency division switching counter and using the logic i...
|
|
JPH0373179B2 |
|
|
JPH03111035U |
|
|
JPH0370935B2 |
PURPOSE:To reduce number of elements and to expand an output amplitude by constituting a circuit converting a signal into a signal having a half frequency so that its output terminal receives a potential of a collector of a transistor (T...
|
|
JPH0352041Y2 |
|
|
JPH0368348B2 |
|
|
JPH03236628A |
PURPOSE: To ensure high speed operation without complicated and large-sized configuration by providing an exclusive OR circuit between a data flip-flop and a changeover circuit so as to generate a pseudo random signal realized by a presc...
|
|
JPH0365053B2 |
An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second dete...
|
|
JPH03227121A |
PURPOSE: To reduce power consumption by halting an FF circuit which generats a frequency division clock with a frequency division ratio larger than that of a frequency division clock selected by a selective signal. CONSTITUTION: When sel...
|
|
JPH03226010A |
PURPOSE: To decrease number of D-FFs and to reduce the circuit scale and power consumption by feeding back an inverting reversed phase output of a final stage D-FF to an input of a 1st stage D-FF. CONSTITUTION: A reversed phase output Q4...
|
|
JPH03224319A |
PURPOSE: To make the 'High' and 'Low' times of an output signal equal by operating two dynamic frequency division circuits at reversal relation mutually, inputting their output signals to a differential amplifier, and setting the output ...
|
|
JPH0361890B2 |
|
|
JPH03217121A |
PURPOSE: To raise the frequency of countable input pulses by inputting the clock input and the output of a flip flop in the preceding stage to a gate circuit and inputting the output of the gate circuit to the clock input of a flip flop ...
|
|
JPH03214631A |
PURPOSE: To prevent a malfunction and an undesired radiation from being caused and to obtain a frequency synthesizer which is small and whose cost is low by a method wherein a prescaler of the frequency synthesizer is constituted in such...
|
|
JPH03211915A |
PURPOSE: To extremely simplify the constitution and to easily vary the frequency division ratio by constituting the fractional frequency divider of a two-modulus frequency divider and a high speed RAM. CONSTITUTION: Switching of a freque...
|
|
JPH0359607B2 |
|
|
JPH03206718A |
PURPOSE: To generate a desired reset signal, to eliminate the need for an external reset input and to decease the number of terminals in a counter circuit by providing a differentiation circuit, an inverting delay element, a monostable m...
|
|
JPH03206721A |
PURPOSE: To easily attain frequency-division of any non-integer number by driving a PN pattern generator with a reference clock and decoding the PN pattern with a decoder. CONSTITUTION: A PN pattern generator 2 is provided where PN patte...
|
|
JPH03206720A |
PURPOSE: To increase only the operating upper limit frequency and to realize a wide frequency division operating frequency range by revising a gate width of a switch FET in the decreasing direction and specifying its maximum value while ...
|
|
JPH0356018B2 |
|
|
JPH03195214A |
PURPOSE: To improve the matching performance of an input output signal in the case of multi-stage connection of frequency dividers by differentiating a threshold voltage of 1st and 2nd transistors(TRs) from a threshold voltage of TRs bei...
|
|
JPH03187522A |
PURPOSE: To always set an exact data value and to obtain the effect of an asynchronization countermeasure by using the output signal of a D flip-flop in addition to a LOAD permitting signal with the same cycle as a data input. CONSTITUTI...
|
|
JPH03185924A |
PURPOSE: To eliminate the need for a reference voltage without using longitudinally stacked gate structure for a feedback gate by using the output of a final stage of plural FFs connected in cascade in place of the reference voltage as t...
|
|
JPH03181223A |
PURPOSE: To reduce the delay time of an output signal to an input signal by providing the 1st - 3rd latch means, and acquiring the binary signal of an input clock signal at the output side of the 2nd latch means. CONSTITUTION: Both a clo...
|
|
JPH03175736A |
PURPOSE: To make it possible to easily generate two kinds or more of clocks from one oscillation circuit by providing the frequency dividing circuit with frequency dividers each of which inputs an output clock from the oscillation circui...
|
|
JPH0349398B2 |
|
|
JPH03171820A |
PURPOSE: To obtain a 2n-1 frequency dividing circuit with a simple constitution by feeding back the NAND output between the Q output of a flip flop in the (n-1)th stage and that in the last stage to the D input of a flip flop in the firs...
|
|
JPH0346917B2 |
|
|
JPH03159317A |
PURPOSE: To accelerate an operation by providing a duty factor control circuit for the clock signal of a counter, and changing the duty factor of a clock. CONSTITUTION: The duty factor control circuit 14 which controls the duty factor of...
|
|
JPH0344693B2 |
|
|
JPH03155219A |
PURPOSE: To obtain a pulse output with high accuracy by generating a carry signal from a frequency division counter based on a frequency setting value set programmably with a microcomputer, and outputting the number of carry signals as p...
|
|
JPH0342818B2 |
|
|
JPH0342817B2 |
|
|
JPH0342819B2 |
|
|
JPH0342814B2 |
|
|
JPH0342815B2 |
|
|
JPH0342816B2 |
|
|
JPH0342528B2 |
|
|
JPH03502753A |
A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing ...
|
|
JPH0340537B2 |
|
|
JPH0339275B2 |
A logic regulation circuit for regulating the frequency dividing ratio of a variable frequency divider of an electronic timepiece comprises a first switch group having a plurality of ON and OFF switching states representative of differen...
|
|
JPH03133213A |
PURPOSE: To improve the allowable power voltage giving effect onto the DC bias of a transfer gate by setting the absolute value of a threshold voltage of the transfer gate to the value multiplied by 1.5 to 3 of the absolute value of the ...
|
|
JPH03132213A |
PURPOSE: To easily and inexpensively obtain a signal with a duty factor of 50% by correcting a part whose duty factor is separated from 50% in the output of a flip-flop based on a signal outputted from the output terminal at a prescribed...
|
|
JPH0337332B2 |
|
|
JPH03131120A |
PURPOSE: To attain frequency division with an optional non-integer frequency dividing circuit of the same constitution as an integer frequency dividing circuit by adding a non-integer frequency division ratio utilizing the processing of ...
|
|
JPH03128529A |
PURPOSE: To prevent deviation from being generated totally even in the case of preparing a frequency not to be just divided by an original clock or the clock of a frequency to be a recurring decimal by outputting a trigger every time the...
|
|
JPH0325227Y2 |
|
