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JPH05504875A |
A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple freq...
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JPH0548008B2 |
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JPH05175836A |
PURPOSE: To simplify the configuration of a frequency divider circuit and to enable high frequency division. CONSTITUTION: An inverter 9 is provided to invert a ripple carry signal 12 of a pulse counter 7 in a programmable counter 17, an...
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JPH05175829A |
PURPOSE: To provide the method and the device for input and output which can read and write data at a high speed. CONSTITUTION: The high-speed operation is possible if a counter 1 is used where D flip flops are inserted to the series car...
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JPH05175830A |
PURPOSE: To provide the counter circuit which is operated regardless of disappearance of a load pulse (LD) and is operated in accordance with the deviated load pulse LD in the case of deviation of LD from the initial LD. CONSTITUTION: Th...
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JPH05175831A |
PURPOSE: To provide a high-speed counter having a high operating frequency and the method of use. CONSTITUTION: In the synchronous counter where flip flops FF0 to FF3 whose number corresponds to the number of bits and the same number of ...
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JPH05175833A |
PURPOSE: To set a variable step width of the phase of an output signal with a small-scale and simple circuit by providing a counter, a comparing means, and an output control means. CONSTITUTION: A counter 11 divides the frequency of an i...
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JPH0544204B2 |
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JPH05160721A |
PURPOSE: To use a frequency divider circuit whose frequency division ratio is selected with a simple circuit and to attain circuit integration inexpensively with high general-purpose performance by closing a gate circuit with a pulse ext...
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JPH05160722A |
PURPOSE: To obtain a digital frequency divider circuit in which accurate frequency division is implemented and its configuration is simplified through adoption of complete digital system. CONSTITUTION: A frequency divider circuit impleme...
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JPH0548437U |
[Purpose] To realize a frequency multiplication circuit that does not cause jitter in the output value. [Constitution] A first frequency divider circuit that divides the input pulse signal into 1/2 frequency signals, a second frequency d...
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JPH05152938A |
PURPOSE: To form a more accurate object frequency by changing the number of programs with a specific count value so as to implement correction when the optional object frequency is generated with a counter comprising a ring counter and a...
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JPH05152939A |
PURPOSE: To implement a level shift to a base of an input transistor-(TR) without occurrence of an operation delay by inserting a resistive element in a load circuit of a preamplifier and connecting a base of an input TR of a flip-flop t...
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JPH05145408A |
PURPOSE: To increase the counting processing speed by grouping multi-bit data and applying the counting processing only to the lower-order group so as to decrease a maximum carrier propagation delay corresponding to a bit number in the g...
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JPH0522875Y2 |
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JPH05142986A |
PURPOSE: To fairly evaluate singers, speakers, or plays in a song, speech, or play contest so that many people agree. CONSTITUTION: When evaluation points for, for example, the singer to be evaluated are inputted on terminal devices 1 di...
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JPH05136690A |
PURPOSE: To send/receive an accurate timing of data processed with a clock whose frequency division ratio is different by resetting a frequency divider circuit to take synchronization so that an ANDing clock of frequency divider clocks o...
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JPH05136691A |
PURPOSE: To obtain the synchronizing counter of a multi-bit length operated at a high speed. CONSTITUTION: Outputs of T-FFs 102-104 are subject to re-clock by D-FFs 201-203 and outputs of the D-FFs 201, 202 are given to next-stage T-FF 1...
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JPH0520018Y2 |
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JPH05129936A |
PURPOSE: To obtain the programmable counter easily generating a complicated output waveform which has been difficult to be realized by a conventional system. CONSTITUTION: A counter 2 is operated by setting data of an A data register 4 a...
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JPH05122023A |
PURPOSE: To obtain a novel counter circuit, regarding a semiconductor circuit device. CONSTITUTION: This semiconductor circuit device is provided with a flip-flop circuit part 2 composed of a pair of transistors T6, T7 performing inversi...
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JPH05122020A |
PURPOSE: To obtain a static type transfer gate sequential circuit capable of performing the same high speed operation as a dynamic type and coping with a low speed operation. CONSTITUTION: The static type transfer gate sequential circuit...
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JPH05122021A |
PURPOSE: To obtain a static type transfer gate sequential circuit capable of performing the same high speed operation as a dynamic type and coping with a low speed operation. CONSTITUTION: The static type transfer gate sequential circuit...
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JPH05114856A |
PURPOSE: To provide the dynamic type transfer gate frequency divider which has a faster operation speed than a conventional dynamic type. CONSTITUTION: This dynamic type transfer gate frequency divider has four transfer gates TG1-TG4 fou...
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JPH05114855A |
PURPOSE: To enable the static type transfer gate frequency divider which operates faster than a static type although it can operate at a slow speed as a static type. CONSTITUTION: This static type transfer gate frequency divider has four...
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JPH0530087B2 |
PURPOSE:To attain high speed output signal by constituting the output section by a bipolar transistor(TR) and giving an output signal with an opposite polarity to the input signal according to the 1st and 2nd clock signals and holding th...
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JPH0516741Y2 |
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JPH0516494Y2 |
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JPH05102844A |
PURPOSE: To provide the frequency divider circuit able to frequency-divide a frequency of an input signal into 1/10 or 1/11 in which a delay margin is larger than that of a conventional frequency divider circuit and malfunction at change...
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JPH05102843A |
PURPOSE: To provide the dynamic frequency divider whose clock bias level is stable. CONSTITUTION: The frequency divider is provided with a differential buffer having 1st and 2nd FETs 1, 2 whose sources are connected in common to form a d...
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JPH0528007B2 |
An integrated divide-by-two frequency divider circuit in BFL logic of the master-slave flip-flop type which comprises two complementary outputs Q and &upbar& Q and only a single input for a control signal. The divider is formed only by N...
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JPH0531364U |
[Purpose] Pulse generation circuit that operates when the power supply voltage drops [Constitution] The signal A generated by the oscillator circuit 1 becomes the input of the frequency divider circuit 2. The frequency dividing circuit 2...
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JPH0595281A |
PURPOSE: To obtain the clocked CMOS frequency divider operated at a higher speed than that of a dynamic type frequency divider regardless of the static type frequency divider. CONSTITUTION: A memory function by inverters V1, V2 or V3, V4...
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JPH0595279A |
PURPOSE: To attain a high operating speed in excess of the speed of a conventional high speed dynamic type circuit by cross-coupling two high speed dynamic frequency dividers so as to make only one gate number included in a critical path...
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JPH0595280A |
PURPOSE: To prevent the mis-count of a counter when only a phase A or B is oscillated with respect to the count method for a biphase pulse. CONSTITUTION: A phase A signal (1) is inputted to an up-gate 12 or a down-gate 13 in the count me...
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JPH0590951A |
PURPOSE: To select a frequency divided output of a small width in the unit of an original clock without remarkable increase in the circuit scale when a desired frequency division ratio is limited to a certain range. CONSTITUTION: An orig...
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JPH0590953A |
PURPOSE: To improve the operating speed of a modulus circuit outputting a mode switching signal used to revise a frequency division number of a prescaler to the prescaler and to reduce the power consumption. CONSTITUTION: An output signa...
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JPH0590920A |
PURPOSE: To provide a pulse control circuit setting uniquely the resolution of a pulse for a register or the like connected to a counter without revising the resolution of the counter especially. CONSTITUTION: The pulse control circuit i...
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JPH0523691B2 |
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JPH0525841U |
[Purpose] In the electronic counter that counts and displays the input pulse, the operation mode of the display is switched between the addition counter and the subtraction counter without interrupting the counting operation during use. ...
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JPH0583124A |
PURPOSE: To obtain the programmable counter with high function by selecting the operating mode in response to a signal from an input terminal and a carry signal and inputting a signal in response to the mode to a data input of a flip- fl...
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JPH0523115B2 |
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JPH0522411B2 |
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JPH0575437A |
PURPOSE: To operate the semiconductor integrated circuit stably at a low voltage even when a constant current transistor(TR) of an ECL gate circuit section is omitted with respect to the semiconductor integrated circuit provided with the...
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JPH0523632U |
[Purpose] Widen the output pulse width by making the duty ratio of the output signal of the 1/3 frequency divider circuit 1: 1. [Constitution] When the input signal A of period T is given to the clock inputs of the first JK flip-flop 1 a...
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JPH0575443A |
PURPOSE: To quicken the operation by feeding back directly a 2nd feedback signal outputted from a 4th transfer gate(TG) of a poststage to 1st and 2nd gate circuits of a pre-stage. CONSTITUTION: The switching of 3rd and 4th gate circuits ...
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JPH0573264A |
PURPOSE: To provide an inexpensive program counter capable of simplifying a circuit configuration and improving the operational speed by reducing the number of transmission gates. CONSTITUTION: First and second transmission gates 1 and 2...
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JPH0516213B2 |
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JPH0548436A |
PURPOSE: To synchronize an output clock with a frame pulse when a value resulting from frequency-dividing a master clock within one period of a frame pulse is non-integer with respect to the clock generating circuit generating a clock re...
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JPH0548432A |
PURPOSE: To provide the 1/3 frequency divider circuit in which no delay element is required, the mount scale is reduced and monolithic processing is easily attained when a 1/3 frequency division clock whose duty ratio is 1:1 is obtained....
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