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WO/2004/100354A1 |
Receiver (20) comprising a mixer (23) with a first input, a second input and one output. An input signal (SRF(t)) comprising a high frequency component fRF is applied to the first input, and a local oscillator signal (SLOnew(t)) is appli...
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WO/2004/098043A2 |
Mixer-systems comprising gain-blocks (1-4) and switches (5-8) have a flexibility depending upon their configuration (insight) and are made more flexible (basic idea) by supplying data input signals to the gain-blocks (1-4) and oscillatio...
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WO/2004/098042A2 |
An apparatus comprising an amplifier circuit, a tuning circuit and a mixer circuit. The amplifier circuit may be configured to generate an output signal at a first node in response to an input signal received through a second node. A tun...
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WO/2004/097450A1 |
An apparatus for characterising an input signal within a broad frequency band by comparing the same input signal in a plurality of channels, in order to operate digital Electronic Support Measures (ESM) which require a broad bandwidth to...
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WO/2004/098073A2 |
A conversionless direct detection system for detecting signals having a very large dynamic range, with a virtually unlimited bandwidth utilizes a successive detection approach having successive log amplifier gain stages, with each gain s...
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WO/2004/095082A2 |
An optoelectronic assembly for reducing interference in an optical data stream received over a channel includes a converter, an equalizer, a microcontroller, and a comparator. The converter converts the optical data stream to an electric...
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WO/2004/095235A2 |
A system and method are provided for communicating utilizing a plurality of different communication standards. To accomplish this, included is a single transceiver that utilizes a plurality of different communication standards.
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WO/2004/093322A2 |
A digital PLL includes an adaptive PFD, an adaptive loop filter, an iDAC, an ICO, and a divider. The adaptive PFD receives a reference signal and a feedback signal, determines phase error between the two signals, and provides a PFD value...
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WO/2004/093327A2 |
Receiver architectures and associated methods are disclosed that provide initial analog coarse tuning (102) of desired channels (108) within a received signal spectrum (107), such as a set-top box signal spectrum for satellite communicat...
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WO/2004/088835A1 |
A passive mixer (100) for converting a radio frequency (RF) signal to an intermediary frequency (IF) signal or vice versa. The mixer comprises a voltage controlled mixing means (110) for mixing a local oscillator signal with either an RF...
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WO/2004/086603A1 |
Frequency detector systems (1) comprise phase detector systems (11) for, in response to data signals, generating Q-phase signals and I-phase signals, and comprise frequency detectors (10) for, in response to Q-phase signals and I-phase s...
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WO/2004/086604A1 |
Linear phase detectors comprising circuits (1,2) receiving reference signals (REF) and first and second clock signals (CLK-Q, CLK-I) for generating first and second (phase) control signals (UP,DOWN) for use in multiplier circuits, demodu...
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WO/2004/086605A1 |
Linear phase detectors comprising circuits (1,2) receiving first and second clock signals (CLKOO, CLK90) for generating first and second control signals (UP,DOWN) for use in clock extractors and data regenerators have large delays due to...
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WO/2004/082232A1 |
A transceiver (300) is provided with a compensation scheme for compensating gain and phase mismatches introduced by respective pairs of base-band filters in the receiver (130a, 130b) and transmitter (230a, 230b) of a wireless transceiver...
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WO/2004/082131A1 |
A modulated optical radiation field (I) whose modulation amplitude and temporal phase depend on the local position can be detected with a plurality of pixels 1. Each pixel 1 consists of a transducing stage (T) that converts incoming ligh...
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WO/2004/082189A2 |
A signal receiving apparatus (100) provides a flexible architecture for single or multiple channel reception capability. According to an exemplary embodiment, the signal receiving apparatus (100) includes a front-end processor (20) and o...
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WO/2004/082144A1 |
The phase/frequency comparator (8) consists of two edge-triggered storage elements (13, 14), which are each set by an edge of a reference frequency signal (3) of a phase-locked/frequency-locked loop (1) and by an edge of an output freque...
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WO/2004/082145A1 |
A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (U¿DIV?) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detec...
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WO/2004/082136A1 |
A system and method for controlling amplification of a signal received by a ZIF radio having a power level within a full power range relative to a minimum noise floor. The ZIF radio includes a ZIF receiver front end (101), an overload de...
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WO/2004/079924A2 |
A tuner architecture (100) is disclosed that mixes an analog RF input signal (302) and a digital local oscillator signal (306) to generate a output signal (304) at a desired IF frequency, including low-IF and zero-IF solutions. The tuner...
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WO/2004/077667A2 |
A method of processing an AM radio signal comprises the step of receiving an AM radio signal including an upper sideband portion and a lower sideband portion, demodulating the upper sideband portion and the lower sideband portion to prod...
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WO/2004/075557A1 |
Frames comprise odd fields and even fields. The frame sync segments of the odd fields contains a current map specifying the location of data in frames, a next map specifying the location of data in a future frame, and a frame count desig...
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WO/2004/073159A2 |
The present invention provides systems and methods for parallel interference suppression. A processing engine is used to substantially cancel a plurality of interfering signals within a received signal. The processing engine includes a p...
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WO/2004/070977A1 |
An improved calibration system for a receiver is configured to calibrate the I and Q paths to correct for gain mismatch and quadrature phase errors. In a preferred embodiment, the calibration system calibrates the I and Q paths by using ...
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WO/2004/070939A1 |
A frequency converter having no solid-state devices having nonlinear characteristics and no complex resonator structure and operable in a wide frequency range from microwave frequencies to terahertz wave frequencies. An input section (1)...
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WO2004032339B1 |
A subharmonic mixer (106) and a method of downconverting a received radio frequency signal is described. The subharmonic mixer (106) of the present invention uses two stacks of switching cores (184, 186) with high order symmetry to reduc...
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WO/2004/070940A1 |
A television tuner for tuning analog and digital television signals that requires only one off-chip filter. An integrated first frequency stage up-converts the received signal to a higher frequency. An off-chip filter provides coarse tun...
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WO/2004/068699A1 |
Three-phase mixer-systems comprising at least three groups of mixers (1-4,5-8,9-12,30) for frequency translating signals are (basic idea) provided with balancing means (13-21,31) for suppressing certain mixing products with harmonics of ...
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WO/2004/068778A2 |
Tunable upconversion mixers (200) that have a controllable pass-band response and provide substantial image rejection, making costly post-mixing filtering at least optional, if not unnecessary for many applications. A single mixer is abl...
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WO/2004/066074A2 |
A clock recovery circuit and a high speed phase detector circuit that operate at a clock speed equal to one-half the input data rate (i.e., a half-rate clock) are presented. The clock recovery circuit uses dual input latches to sample th...
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WO/2004/066512A1 |
The system for downward mixing an input signal into an output signal comprises: a device (401) for producing a first receive signal (4011) and a second receive signal (4013) on a first intermediate frequency; a converter device (403) for...
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WO/2004/063851A2 |
Methods and apparatus for sending information to a target mobile station include compressing the header portion of short data burst messages before being sent to the target mobile stations, and decompressing the header portion of the rec...
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WO/2004/064246A1 |
The present invention relates generally to communications, and more specifically to a method and apparatus for generating local oscillator signals used for up- and down-conversion of RF (radio frequency) signals. A major problem in the d...
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WO/2004/062087A1 |
The present invention relates generally to communications, and more specifically to a method and apparatus of modulating baseband and RF (radio frequency) signals. A modulator topology is disclosed in which an input signal x(t) is up-con...
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WO/2004/059846A1 |
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is res...
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WO/2004/057752A1 |
Mixer-systems (1) comprising mixer-circuits (2) with mixers (3) for frequency translating signals comprising audio/video information and for use in mobile phones or television receivers are provided with amplitude detectors (6) for makin...
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WO/2004/057768A1 |
A direct conversion transmission circuit preferable to a mobile communication device. The transmission circuit is adapted to the variable range of the signal output level required for W-CDMA, does not need any high-performance low-noise ...
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WO/2004/057753A1 |
A Gilbert cell (Q3-Q8) of a mixer (11) controls a differential output voltage between a pair of output terminals (OUT1, OUT2) of the mixer (11). A polysilicon resistor (R7) of the mixer (11) applies a differential loading to the differen...
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WO/2004/057770A1 |
An RF front-end receiver comprises a low noise amplifier (LNA) and a local oscillator driver (LOD), which are connected to respective input ports of a mixer. The mixer comprises a first and a second transistor (M3, M6) having their gates...
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WO/2004/055995A2 |
The present invention is directed to a system and method of reducing frequency interference in a circuit when the harmonics of at least two frequencies could cause interference when such harmonics interact with each other. In one embodim...
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WO/2004/055970A1 |
In an activation signal output circuit having an RF/DC converting circuit for receiving a high frequency power (RF) of a particular frequency to output a DC potential (DC), there is provided a detecting/amplifying part (210) comprising a...
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WO/2004/054128A2 |
Multiple input signal sources in predetermined frequency bands are each applied to block frequency converters. Each block frequency converter frequency converts an input signal to one of a plurality of predetermined frequency bands. A cr...
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WO/2004/054165A1 |
A phase comparator circuit, particularly, a phase erroneous-synchronization detecting circuit for detecting a phase erroneous-synchronization occurring when the duty of data deviates from a hundred percent in comparison of phase differen...
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WO/2004/054145A2 |
A cascadable AGC amplifier in a signal distribution system includes a low noise cascadable amplifier having a through path and a cascadable output. The cascadable amplifier is also configured to provide AGC over a predetermined input pow...
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WO/2004/054312A2 |
An NxM crosspoint switch allows a signal from any one of the N inputs to be routed to one or more of the M crosspoint switch outputs. The switches within the crosspoint switch can be configured as voltage mode or current mode switches. I...
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WO/2004/054092A1 |
Mixer-systems for up/down-converting frequencies comprise many components: in case of balanced quadrature conversion, some parts will show a fourfold repetition (insight). By creating a three-phase mixer-system (10,40), less components w...
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WO/2004/051550A1 |
A circuit (48) includes an input terminal adapted to receive an input voltage (VRF), a MOSFET (16) having its drain terminal (20) and its source terminal (18) connected together, a first switching arrangement (30) configured to be contro...
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WO2004036811A9 |
The present invention is directed to signal cancellation in spread spectrum communication systems. In particular, the present invention provides method and apparatus for selectively canceling interfering signals, even where symbols to be...
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WO/2004/047411A1 |
In order to compensate for performance degradation caused by inferior low-cost analog radio component (105) tolerances of an analog radio (100), a future system architecture (FSA) wireless communication transceiver employs numerous digit...
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WO/2004/045091A2 |
A frequency agile sequential amplifier circuit that includes first and second RF amplifiers (16, 18) coupled by a SAW delay line (20), a double balanced mixer (17) coupling the first RF amplifier (16) to the SAW delay line (20), the outp...
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