| Document |
Document Title |
|
WO/2023/157754A1 |
In the present invention, a 1-port SRAM cell is provided with: a load transistor (PU1); a load transistor (PU2); a drive transistor (PD1); a drive transistor (PD2); an access transistor (PG1) of which one node is connected to an embedded...
|
|
WO/2023/156578A1 |
The present invention relates to the field of digital processing in order to reproduce the auditory impression of a "vinyl sound". Vinyl records were created in 1948; the sound information was reproduced by the movement of a needle trans...
|
|
WO/2023/158450A1 |
When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and ...
|
|
WO/2023/155139A1 |
A method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line b...
|
|
WO/2023/158330A1 |
A computer-implemented method for recording, comprising: transcribing a content of a conference session using a conferencing system, determining a topic from the content of the conference session, determining a timestamp for the topic fr...
|
|
WO/2023/156485A1 |
The invention relates to photopolymer compositions comprising a) matrix polymers, b) writing monomers, c) at least one photoinitiator system, d) optionally at least one non-photopolymerizable component, e) optionally catalysts, radical s...
|
|
WO/2023/155636A1 |
The present application relates to the technical field of electronic device control, an embodiment thereof provides an electronic device, and the probability of a file system being damaged when UFS is used can be reduced. The electronic ...
|
|
WO/2023/158564A1 |
A SRAM memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capa...
|
|
WO/2023/157724A1 |
The present invention provides a layout structure that, for mask read only memory (ROM), suppresses a reduction in operating speed without an increase in area. This semiconductor memory device comprises: word lines (31, 32) that extend i...
|
|
WO/2023/158730A1 |
A semiconductor device (100) includes a ROM (102), a differential sense amplifier (120) and a multiplexer logic circuit (110). The ROM (102) has memory cells (104) in rows along word lines (108) and columns along bit lines (106), and a r...
|
|
WO/2023/156484A1 |
The invention relates to photopolymer compositions comprising a) matrix polymers, b) writing monomers, c) at least one photoinitiator system, d) optionally at least one non-photopolymerisable component, e) optionally catalysts, radical s...
|
|
WO/2023/152586A1 |
Provided is a semiconductor device that is configured to allow miniaturization and high integration. This semiconductor device includes a memory cell including first to third transistors and a capacitor. The first to third transistors ea...
|
|
WO/2023/153671A1 |
Disclosed is a method for operating ferroelectric-based three-dimensional flash memory including a data storage pattern. According to one embodiment, a program operation method of three-dimensional flash memory may comprise the steps of:...
|
|
WO/2023/151142A1 |
Provided in the present application are a data verification method and apparatus, and an electronic device and a storage medium. The method comprises: reading a storage array to obtain read data, and compressing the read data to obtain f...
|
|
WO/2023/154160A1 |
Sequential assembly of oligonucleotide hairpins is used to create oligonucleotides that encode a specific sequence of arbitrary information. Each oligonucleotide hairpin includes a payload region in the loop region of the hairpin. The pa...
|
|
WO/2023/154155A1 |
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR ...
|
|
WO/2023/153162A1 |
A magnetoresistance effect memory (100) comprises: a magnetoresistance element (11) including a fixed layer (111) in which orientation of magnetization is fixed and a recording layer (113) in which orientation of magnetization changes; a...
|
|
WO/2023/154073A1 |
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a method comprises adjusting a bias voltage applied to one or more non-volatile mem...
|
|
WO/2023/153024A1 |
[Problem] To provide a technique for, for example, writing a servo pattern that can be correctly read even when a data write head is disposed diagonally with respect to the width direction of a magnetic tape. [Solution] A servo recording...
|
|
WO/2023/154596A1 |
A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command from an application processor that indicates a first bank to be...
|
|
WO/2023/154075A1 |
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a system comprises a digital-to-analog converter for receiving an input of k bits a...
|
|
WO/2023/151146A1 |
Embodiments of the present disclosure provide a sense amplification circuit and a semiconductor memory. The sense amplification circuit comprises a discharge circuit and a signal amplification circuit, and the signal amplification circui...
|
|
WO/2023/151149A1 |
The present invention provides a sense amplifier circuit, a control method therefor, and a preparation method therefor. The sense amplifier circuit comprises: a sense amplifier, the sense amplifier being electrically connected to a stora...
|
|
WO/2023/154159A1 |
Sequential assembly of oligonucleotide hairpins is used to create oligonucleotides with specific sequences. Each oligonucleotide hairpin includes a payload region containing one or more nucleotides that are added to the end of an anchor ...
|
|
WO/2023/154192A1 |
A multimodal video generation framework (MMVID) that benefits from text and images provided jointly or separately as input. Quantized representations of videos are utilized with a bidirectional transformer with multiple modalities as inp...
|
|
WO/2023/153670A1 |
Disclosed is an operation method for a three-dimensional flash memory including a ferroelectric-based data storage pattern and a back gate. According to an embodiment, the operation method for a program of a three-dimensional flash memor...
|
|
WO/2023/149912A1 |
A non-volatile memory includes memory cells, word lines connected to the memory cells, and a set of regular control gate drivers connected to the word lines. The control gate drivers include different subsets of control gate drivers that...
|
|
WO/2023/147742A1 |
The methods and apparatus of encoding/decoding a slice of point cloud data into/from a bitstream comprise context-based entropy encoding the slice of point cloud data based on entropy context tables. The method comprises: obtaining (310)...
|
|
WO/2023/149516A1 |
The present invention provides a cover which allows for an increase in the degree of freedom in setting of a distance between a fastener and a gasket. A cover 17 is provided with a joining part 29, which performs fastening, on an outer p...
|
|
WO/2023/149604A1 |
Provided is a sound playback apparatus using an image touch, the sound playback apparatus comprising: a box module formed by an assembly operation along a plurality of folding lines; at least one image unit which is arranged on the upper...
|
|
WO/2023/149665A1 |
Disclosed is an audio clock adjustment device for switching an output audio clock signal between a first audio clock signal and a second audio clock signal, wherein each of the first and second audio clock signals has a different clock r...
|
|
WO/2023/148299A1 |
A computer-implemented method of identifying section transition boundaries within an audio track is provided. The method comprises calculating first and second statistical analyses at a plurality of timesteps. The method further comprise...
|
|
WO/2023/150004A1 |
Methods, systems, and media for presenting user comments containing timed references in synchronization with a media, content item are provided. In some embodiments, a method for presenting user comments during media playback that includ...
|
|
WO/2023/149770A1 |
According to various embodiments, an electronic device comprises: a memory including a first area and a second area which have different logical addresses from each other; and at least one processor connected to the memory. The at least ...
|
|
WO/2023/148196A1 |
The present invention relates to a non-volatile field-effect transistor (10), comprising: - a gate electrode including a first contact (C1); - a source (14) comprising a second contact (C2); - a drain (16) including a third contact (C3);...
|
|
WO/2023/149897A1 |
This specification describes memory controllers with adaptive precharge scheduling. In one aspect, a memory controller includes a refresh scheduler configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRA...
|
|
WO/2023/149670A1 |
A non-volatile memory device according to various embodiments of the present invention comprises: a substrate; a first electrode disposed on the substrate; an insulating film in contact with the first electrode; a semiconductor layer in ...
|
|
WO/2023/149019A1 |
Provided is a magnetic storage device 10 comprising: a magnetoresistive element 11 having a structure in which a recording layer 13 that includes a first magnetic layer, a tunnel barrier layer 14, and a reference layer 15 that includes a...
|
|
WO/2023/147881A1 |
The present invention relates to a method for recording data in a layer of a ceramic material and to a device for recording and reading data in a layer of a ceramic material.
|
|
WO/2023/149418A1 |
A non-volatile memory device (1) comprises: a memory element (4) capable of executing a program operation; a switch (9) including a first end to which an application end of a first power-supply voltage (VDD) is connected; an even number ...
|
|
WO/2023/146573A1 |
A heat‑assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) and a main magnetic pole that has a step or recess in the NFT-facing surface near the GBS t...
|
|
WO/2023/146571A1 |
A heat assisted magnetic recording (HAMR) write head includes a main pole, a waveguide, at least one dielectric matrix layer, and a near-field transducer disposed between the waveguide and the main pole. The near-field transducer is embe...
|
|
WO/2023/142208A1 |
The present invention relates to the field of semiconductor circuit design, in particular to an amplification circuit, a control method, and a memory. The amplification circuit comprises: a sensing amplification circuit (101), comprising...
|
|
WO/2023/142429A1 |
Provided in the embodiments of the present application are a method for predicting an uncorrectable error of a volatile storage medium, and a related device. The method comprises: acquiring an operation information set of a volatile stor...
|
|
WO/2023/142495A1 |
The present invention provides a pre-charging method and a memory device using same. The pre-charging method comprises the following steps: step 1, pre-charging all bit lines; and step 2, setting the voltages of the bit lines according t...
|
|
WO/2023/146611A1 |
A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variabl...
|
|
WO/2023/142207A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular, to an amplification circuit, a control method, and a memory. A sensing amplification circuit (101) comprises a read-out node, a complementary...
|
|
WO/2023/145625A1 |
Provided is a perfluoropolyether compound that is highly soluble in fluorinated solvents, has high heat resistance and shows a strong interaction with magnetic disks. A perfluoropolyether compound that has a structure represented by form...
|
|
WO/2023/144279A1 |
The present technology can provide a mechanism for adjusting a visual effect that is associated with an audio artifact at a given frequency bandwidth that is attenuated by speaker characteristics. The intensity of the visual effects that...
|
|
WO/2023/146567A1 |
Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples...
|
