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WO/2023/178848A1 |
Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory. The signal sampling circuit comprises: an input sampling circuit, used for separately performing sampling processing on a first chip sele...
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WO/2023/178781A1 |
Provided are a control circuit and a semiconductor memory. The control circuit comprises a bias module, which is configured to provide a bias current to a functional module and comprises a first bias module and a second bias module, wher...
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WO/2023/178805A1 |
Embodiments of the present invention provide a signal sampling circuit and a semiconductor memory. The signal sampling circuit comprises: a signal input circuit, which is used for determining an instruction signal to be processed and a c...
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WO/2023/180830A1 |
The invention is directed to a method of processing data in-memory. The method applies electrical signals to at least two input lines, which correspond to at least two rows. These two rows include at least one of the K rows and at least ...
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WO/2023/178828A1 |
An induction boundary determination method for an induction amplifier, an induction boundary determination apparatus for an induction amplifier, a computer-readable storage medium and an electronic device, which relate to the technical f...
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WO/2023/182931A2 |
A photonic device comprising: one or more electrodes configured for voltage application to manipulate an electric field; a ferroelectric material electrically polarizable into a plurality of states through the manipulation of the electri...
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WO/2023/178780A1 |
Embodiments of the present disclosure provide a control circuit and a semiconductor memory. The control circuit comprises a bias switching circuit and a first logic gate circuit; the first logic gate circuit is composed of at least one t...
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WO/2023/178791A1 |
A signal sampling circuit and a semiconductor memory. The signal sampling circuit comprises: a signal input circuit, which is used for determining an instruction signal to be processed and a chip selection signal to be processed; a mode ...
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WO/2023/179529A1 |
A computer-implemented method for unoptimized tape drive read detection is disclosed. The computer-implemented includes determining whether a read order of a trio of related files is consistent with an order in which the trio of related ...
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WO/2023/180058A1 |
Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell disposed on the backside o...
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WO/2023/183391A1 |
A write circuit for writing state into a plurality of superconducting memory cells includes a control circuit, a plurality of write lines, each of the write lines being associated with a corresponding column of the superconducting memory...
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WO/2023/183145A1 |
A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes th...
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WO/2023/178989A1 |
Disclosed in the present invention is a self-alignment control circuit for an offset cancellation calibration circuit of an input buffer. A plurality of timing control signals are generated on the basis of a start signal by means of a de...
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WO/2023/178829A1 |
The present disclosure relates to the technical field of integrated circuits. Disclosed are a method for determining a sense boundary of a sense amplifier, an apparatus for determining a sense boundary of a sense amplifier, a computer re...
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WO/2023/181892A1 |
A memory controller according to one aspect of the present disclosure controls a read operation for a nonvolatile memory cell array unit, and includes a detection unit and a control unit. The detection unit detects the number of bits in ...
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WO/2023/178783A1 |
The present disclosure discloses a skyrmion transistor and a skyrmion transistor control method. The transistor comprises: a ferromagnetic nanotube (101); a write magnetic tunnel junction (102) and a read magnetic tunnel junction (103), ...
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WO/2023/173867A1 |
A page buffer includes a first charge/discharge circuit and a second charge/discharge circuit coupled to a bit line. The first charge/discharge circuit is configured to store first bit line forcing information and apply a first bit line ...
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WO/2023/177795A1 |
A device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a set of quantum dot structures, each quantum dot structure of the set of quantum dot structures including a semiconductor mater...
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WO/2023/175730A1 |
A semiconductor memory device (1) comprises: a memory cell array (3) in which a plurality of memory cells (MC) are connected to a bit line pair (BLT); and a write circuit that sets a bit line on a low potential side to a negative potenti...
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WO/2023/176595A1 |
Provided is a magnetic recording medium that makes it possible to obtain satisfactory electromagnetic conversion characteristics and suppress increases in friction. This magnetic recording medium is a tape-like magnetic recording mediu...
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WO/2023/177671A1 |
An electronic device can be configured to enable a host to indirectly control testing associated with the electronic device. The interface between the host and the electronic device can be abstract, such that the host does not have direc...
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WO/2023/176724A1 |
A non-volatile memory device (1) comprises: a memory element (82) that can carry out a program operation by trapping an electric charge in a sidewall; and a switch (12) that is for expanding a voltage between a drain and a source of the ...
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WO/2023/175552A1 |
The invention consists of a method for generating an extract of significant steps of a video footage representative of the performance of a surgical operation or complex diagnostic investigation produced by a medical recorder 100 and dis...
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WO/2023/173608A1 |
An anti-fuse memory array circuit and an operation method therefor, and a memory. The anti-fuse memory array circuit comprises: at least one anti-fuse memory array (10), the anti-fuse memory array comprising multiple anti-fuse memory cel...
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WO/2023/173259A1 |
Provided are a shift register unit and a driving method therefor, a gate driving circuit, and a display device, relating to the technical field of display. An output circuit in the shift register unit may control, on the basis of a poten...
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WO/2023/173530A1 |
A convolution operation accelerator and a convolution operation method, relating to the field of microelectronic devices. Each word line electrode connects one column of non-volatile memory cells in non-volatile memory cells arranged in ...
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WO/2023/173636A1 |
An electronic device and a driving method therefor. The electronic device comprises a sense amplifier (SA) and a voltage regulation circuit (6). The sense amplifier (SA) comprises a first P-type transistor (PM1), a second P-type transist...
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WO/2023/177864A1 |
Methods and systems for encoding digital information in nucleic acid (e.g., deoxyribonucleic acid) molecules without base-by-base synthesis, by encoding bit-value information in the presence or absence of unique nucleic acid sequences wi...
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WO/2023/175684A1 |
Provided are a convenient memory system, a control method therefor, and an information processing device. A memory system 100 according to an embodiment comprises: a non-volatile memory 2 that has memory cells capable of storing user d...
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WO/2023/173492A1 |
The present application discloses a shift register, a gate driving circuit, and a display device. According to the shift register of the present application, when a pull-up node is at a low level, a first noise reduction module is contro...
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WO/2023/174609A1 |
The invention relates to a provisioning control apparatus (140) configured to be coupled to a provisioning apparatus (160), wherein the provisioning apparatus (160) is electrically connectable with a plurality of pins of an electronic co...
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WO/2023/177531A1 |
A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through...
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WO/2023/176510A1 |
A non-volatile memory device (1) comprises: a first current mirror (8) which has a reference element (81) that is configured as a memory element capable of executing a program operation and a data element (82) that is configured as the m...
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WO/2023/173983A1 |
Disclosed in the embodiments of the present application are a storage apparatus and a related instruction delay statistical analysis method. The storage apparatus is characterized in that the storage apparatus is used for: receiving N op...
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WO/2023/172581A1 |
Methods and systems for determining past and future cycles of scenes that employ looping functions are disclosed. In one embodiment, a scene that includes a repeating segment may be created. The repeating segment may have a finite durati...
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WO/2023/170172A1 |
A resistive switching memory device comprises an active layer comprising an ionic conducting material. The active layer is disposed on a substrate. The device further comprises: a first electrode, a second electrode and optionally a firs...
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WO/2023/168817A1 |
A test method for a memory chip, a test apparatus for a memory chip, a computer readable storage medium and an electronic device, belonging to the technical field of semiconductors. The method comprises: determining a memory block corres...
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WO/2023/172398A1 |
One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, eac...
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WO/2023/169075A1 |
The present application relates to the technical field of data storage, and particularly to a read-write circuit, a read-write method, and a ferroelectric memory. The read-write circuit comprises: a sensitive amplifier, which is coupled ...
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WO/2023/172755A1 |
A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level...
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WO/2023/169420A1 |
The present invention provides a memory control system and method. The system comprises: a memory which comprises a main storage module and a built-in EEPROM; a storage controller which, in a normal mode, reads a program in the main stor...
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WO/2023/171824A1 |
A discoidal glass substrate (1) manufacturing method includes: preparing a discoidal glass blank having main surfaces (11a, 11b) and an outer circumferential edge surface (12); and projecting laser light (L) more than once around the out...
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WO/2023/168727A1 |
A repair system (100) and repair method for a semiconductor structure, and a storage medium and an electronic device. The semiconductor structure comprises a main storage area and a redundant storage area. The repair system (100) compris...
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WO/2023/170816A1 |
This magnetic array comprises: a plurality of magnetoresistance effect elements; and a pulse application device that applies a pulse to at least one of the plurality of magnetoresistance effect elements. Each of the plurality of magnetor...
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WO/2023/171683A1 |
This neural network arithmetic circuit holds a plurality of coupling weight coefficients corresponding respectively to a plurality of input data pieces, and outputs output data in accordance with the results of product-sum operations bet...
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WO/2023/168847A1 |
Provided in the present disclosure are a testing circuit and method for a memory chip. The testing circuit for a memory chip comprises: a data reading apparatus, which reads word line data stored in all repositories of a memory under tes...
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WO/2023/168806A1 |
A memory failure testing method, a memory failure testing apparatus, a computer-readable storage medium, and an electronic device. The memory failure testing method comprises: writing preset storage data into a storage array of a memory ...
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WO/2023/172757A1 |
Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whethe...
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WO/2023/171452A1 |
According to the present invention, a two-port SRAM comprises load transistors (PU1, PU2), drive transistors (PD1, PD2), access transistors (PG1, PG2), a read drive transistor (RPD), and a read access transistor (RPG). Embedded wires (11...
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WO/2023/171402A1 |
A storage device (500) according to an embodiment of the present disclosure comprises: a first memory (501) that allows data reading/writing; a second memory (502) that allows data reading/writing; a detection unit (504) that detects mag...
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