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Patent Searching and Data


Matches 651 - 700 out of 857,845

Document Document Title
WO/2018/221044A1
A semiconductor device of the present disclosure is provided with: a plurality of first selection lines that are provided in a region, which is outside a region of a plurality of opening areas and is in a first area, on a first selection...  
WO/2018/222686A1
Disclosed are systems, methods, and computer-readable storage media to provide voice driven dynamic menus. One aspect disclosed is a method including receiving, by an electronic device, video data and audio data, displaying, by the elect...  
WO/2018/216499A1
The present technology relates to a data processing device, a data processing method, a program, and data processing system for enabling meaningful audio to be recorded for intermittently-captured images. The data processing device is pr...  
WO/2018/216542A1
The present invention implements a gate driver (scanning signal line driving circuit) having higher reliability than conventional ones. A shift register constituting the gate driver operates on the basis of gate clock signals of three or...  
WO/2018/215715A1
The invention relates to a memory device comprising one or more banks (126), each bank comprising a plurality of memory rows, the memory device comprising moreover: logic for detecting triggering of the Row Hammer (123) and configured to...  
WO/2018/217632A1
A bipartite memristive network and method of teaching such a network is described herein. In one example case, the memristive network can include a number of nanofibers, wherein each nanofiber comprises a metallic core and a memristive s...  
WO/2018/217582A3
Apparatuses and methods for detecting refresh starvation at a memory. An example apparatus may include a plurality of memory cells, and a control circuit configured to monitor refresh request commands and to perform an action that preven...  
WO/2018/217744A1
A memory device includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to iteratively: determine a first error rate corresponding to a current processing lev...  
WO/2018/217813A3
Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to...  
WO/2018/215804A1
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS e...  
WO/2018/214613A1
Disclosed are a shift register circuit and a drive method therefor, and a gate drive circuit and a display panel. The shift register circuit comprises: an input circuit (1), a first control circuit (2), a second control circuit (3), a th...  
WO/2018/217737A2
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the backg...  
WO/2018/217425A1
A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die...  
WO/2018/217737A3
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the backg...  
WO/2018/217899A1
An example system (600) includes a non-volatile memory (606) including a binary section (615), a first page table (610) and a second page table (612). The system (600) also has a volatile memory (616) and a processor (604) coupled to the...  
WO/2018/217740A1
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the dis...  
WO/2018/217311A1
Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and ...  
WO/2018/216424A1
Provided is a configuration that allows rapid confirmation of whether medium-recorded MMT format audio data is MPEG4 AAC LC audio data or MPEG4 ALS audio data. A clip information file in which audio identification information is recorded...  
WO/2018/216365A1
A semiconductor device according to the present disclosure comprises: a plurality of first selection lines provided in a first region, and extending in a first direction and aligned in a second direction; a plurality of second selection ...  
WO/2018/217467A1
An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O...  
WO/2018/217813A2
Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to...  
WO/2018/211378A1
The present invention provides a novel semiconductor device. Alternatively, the present invention provides a storage device that is capable of holding more multivalue information. One among the source and the drain of a write transistor ...  
WO/2018/213073A3
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an...  
WO/2018/212013A1
An information processing device operates in an apparatus provided with a display unit, and causes the display unit to display a plurality of specific frame images constituting a moving image having a data size smaller than a moving imag...  
WO/2018/212082A1
A memory device according to one embodiment comprises a memory cell. The memory cell includes: a variable resistance element the resistance state of which changes between a first resistance state and a second resistance state; and a sele...  
WO/2018/213399A1
An integrated circuit device for reservoir computing can include a weighted input layer, an unweighted, asynchronous, internal recurrent neural network made up of nodes having binary weighting, and a weighted output layer. Weighting of o...  
WO/2018/211326A1
A new watermarking concept is presented. The method exploits audio fingerprinting in order to reuse the same watermark payloads between audio copies originating from different audio masters. This is achieved by using fingerprints of audi...  
WO/2018/212892A1
Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signa...  
WO/2018/211613A1
The present invention relates to an encoded video reproduction device that is provided with: a stream separation unit that separates, from a stream information file, video information and audio information and divides each of the video i...  
WO/2018/211320A1
A technique relates to a superconducting chip. Resonant units each include a Josephson junction. The resonant units have resonant frequencies whose differences are based on a variation in the Josephson junction. A transmission medium is ...  
WO/2018/213184A1
A data stream comprising a plurality of data records is retrieved. Portions of the data stream are aggregated to form a plurality of record packets of a predetermined size capacity. Each of the plurality of record packets comprises a num...  
WO/2018/212056A1
A semiconductor circuit according to the present disclosure includes: a first circuit capable of applying an inverted voltage of a voltage at a first node to a second node; a second circuit capable of applying an inverted voltage of a vo...  
WO/2018/208584A3
The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are great...  
WO/2018/207523A1
An aluminum alloy substrate for magnetic disks, which is characterized by being formed of an aluminum alloy that contains 0.4-3.0 mass% of Fe with the balance made up of Al and unavoidable impurities, and which is also characterized in t...  
WO/2018/208791A1
A method for detecting defects in objects includes: controlling, by a processor, one or more depth cameras to capture a plurality of depth images of a target object; computing, by the processor, a three-dimensional (3-D) model of the tar...  
WO/2018/206920A1
The present techniques generally relate to correlated electron switch elements, and may relate more particularly to sensing impedance states of correlated electron switch elements.  
WO/2018/206556A1
The invention relates to a layer structure comprising a curable protective layer C and a photopolymer layer B, a method for producing such a layer structure, a method for producing a hologram using said layer structure, a sealed holograp...  
WO/2018/208445A1
Apparatuses for signal boost are disclosed, an example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digi...  
WO/2018/205543A1
A shift register, a method for driving same, a gate integrated drive circuit and a display device. The shift register comprises an input control circuit (101), a first output control circuit (102), a pull-up control circuit (103), a firs...  
WO/2018/207618A1
The present invention relates to a read-only optical information recording medium in which at least one reflection film and at least one optically transparent layer are stacked sequentially on a substrate and with which information is pl...  
WO/2018/208881A1
Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cel...  
WO/2018/208584A2
The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are great...  
WO/2018/205322A1
A shift element temporary storage circuit, a waveform generation method thereof, and a display panel applying same. The shift element temporary storage circuit comprises: a multi-stage shift register (300) including: a first switch (T10)...  
WO/2018/208385A1
Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data rec...  
WO/2018/206921A1
The present techniques generally relate to correlated electron switch elements and, more particularly, to controlling current through correlated electron switch elements during programming operations.  
WO/2018/206498A1
The invention relates to a sealed holographic medium comprising a layer structure B'-C1'-C2', a method for producing the sealed holographic medium, a kit of parts, a layer structure comprising a protective layer and a substrate layer, an...  
WO/2018/206503A1
The invention relates to a holographic medium containing a layer structure comprising a curable protective layer C and a photopolymer layer B, a method for producing a holographic medium of this kind, a method for producing a hologram us...  
WO/2018/206955A1
The present techniques generally relate to methods, systems and devices for operation of correlated electron switch (CES) devices. In one embodiment, a CES device may be placed in any one of multiple impedance states in a write operation...  
WO/2018/207353A1
A reconfigurable circuit comprising: a complementary resistive switch; a write circuit to configure the complementary resistive switch; a read circuit to get ON/OFF information of the complementary resistive switch; a register to store O...  
WO/2018/204755A1
A system and a method for the deterministic generation of magnetic skyrmions includes a magnetic strip configured to store and transport skyrmions. The magnetic strip includes one or more spatial inhomogeneities configured to generate a ...  

Matches 651 - 700 out of 857,845