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Patent Searching and Data


Matches 651 - 700 out of 861,271

Document Document Title
WO/2020/015095A1
Disclosed are a shift register (30), a display panel (10) and a method for driving the shift register (30). The shift register (30) in the display panel (10) comprises a control module (56) and a pull-down maintaining module (58), the pu...  
WO/2020/015547A1
A shift register unit (10), a driving method therefor, a gate driving circuit (20) and a display device (30). The shift register unit (10) comprises a blanking input circuit (100), a display input circuit (200) and an output circuit (300...  
WO/2020/018654A2
An approach to a reduced-head hard disk drive (HDD) involves an actuator subsystem that includes a ball screw cam assembly wherein the number of starts of a multi-start screw equals the number of balls riding in a corresponding start. A ...  
WO/2020/015130A1
Disclosed is a method for rapidly detecting a defect in a flash memory. The method comprises the following steps: A. writing test data with a full byte 0x55 into a data register of a flash memory; B. reading the test data from the data r...  
WO/2020/015132A1
Disclosed in the present invention is a method for automatically determining the data rate of tested flash memory, comprising a control chip, flash memory and a software program module, and comprising: the control chip being is signal co...  
WO/2020/018664A2
An approach to a reduced-head hard disk drive (HDD) involves an actuator subsystem that includes a ball screw cam assembly wherein the number of starts of a multi-start screw equals the number of balls riding in a corresponding start. A ...  
WO/2019/229130A3
The invention relates to a resistive memory cell, which is characterized by the following general structure: i) a first electrode; ii) a second electrode; and iii) at least one polyoxovanadate as a discrete molecule (= individual molecul...  
WO/2020/015206A1
Disclosed are a gate driving circuit structure, a display panel, and a driving method for the gate driving circuit structure. In the display panel applied to gate driver on array technology, a shift register is additionally provided with...  
WO/2020/018376A1
A method and corresponding system and non-transitory computer readable medium storing instructions configured to cause a processor to execute steps, are provided to introduce an auxiliary transformation to a digital media, resulting in a...  
WO/2020/016821A1
A method is described for the creation of interactive audio -video contents, through visualization on an interactive display, comprising the following steps: - providing at least one set of interconnected video segments (101), adapted to...  
WO/2020/018234A1
In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from t...  
WO/2020/017233A1
A configuration is achieved, when using recorded content on an information recording medium, with which it is possible to perform a process according to usage control information succeeding usage control information distributed by a broa...  
WO/2020/015569A1
A shift register unit (100), a gate driving circuit (10), a display apparatus (1), and a driving method. The shift register unit (100) comprises an input circuit (110), a first control circuit and an output circuit (130), wherein the inp...  
WO/2020/015125A1
A high, medium, low-order flash memory classification method, comprising the following steps: first, using a method for automatically determining and testing a flash memory data rate, and setting a double data rate or a single data rate ...  
WO/2020/018624A1
A new type of two-terminal magnetic memory device, referred to as antiferromagnetic voltage-controlled memory (AVM) device is disclosed. Antiferromagnetic (AFM) materials have zero magnetization, which makes it immune to external magneti...  
WO/2020/018854A1
An approach to a reduced-head hard disk drive (HDD) involves a load/unload (LUL) ramp subsystem that includes a ramp assembly that includes a rotatable latch link configured for mechanical interaction with a head-stack assembly (HSA) and...  
WO/2020/015124A1
Disclosed is a method for detecting a block with an instable electrical property in a flash memory, the method relating to a control chip (1), a software program module (2) and a flash memory chip (3), wherein the control chip (1) is in ...  
WO/2020/018827A1
First data units can be sampled from a set of data units of a memory component. The first data units can be a subset of the set of data units. An initial data unit is determined from the first data units as a first candidate data unit ba...  
WO/2020/015398A1
A display device (10, 12) and a shift register circuit thereof, wherein the shift register circuit comprises a plurality of stages of shift register (3), and any stage of the shift register (3) comprises the following modules: an input m...  
WO/2020/018218A1
Superconducting logic arrays, SLAs, and field-programmable gate arrays, FPGAs that are based on Josephson transmission lines, JTLs, accommodate reciprocal quantum logic, RQL, compliant binary input signals and provide RQL-compliant outpu...  
WO/2020/018639A1
A computer-implemented method includes receiving a request from a client computing device for a first shot included in a media title being streamed to the client computing device for playback; in response to the request, sending the firs...  
WO/2020/013933A1
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors (2282), reference memory cells, and flash memory cells (2284) during a read operatio...  
WO/2020/011034A1
A system-in-package (SiP) assembly is disclosed, which comprises: a dynamic memory; a non-volatile memory configured to store a scrambling algorithm for the dynamic memory; and a logic processor connected to the dynamic memory and the no...  
WO/2019/152211A9
Disclosed is a system and method for providing program verify adaptation for flash memory. The method includes performing an adjustment iteration, which includes accessing error counts for respective N states of a plurality of memory cel...  
WO/2020/011308A1
The invention relates to a magnetic head (1) having at least one magnetic flux guide (2) with at least two co-operating pole shanks (3), wherein the pole shanks (3) have pole shank ends (4) facing one another and a working gap (5) is for...  
WO/2020/014604A1
An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection opera...  
WO/2020/012470A1
An FD-SOI GC-ed RAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal...  
WO/2020/012551A1
The present invention achieves high-speed recording while reducing the cost of a device relating to optical recording and reading. Provided is an optical recording device that records the interference pattern between signal light and ref...  
WO/2020/014478A1
A nanostructured cross-wire memory architecture is provided that can interface with conventional semiconductor technologies and be electrically accessed and read. The architecture links lower and upper sets of generally parallel nanowire...  
WO/2020/013934A1
Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation ...  
WO/2020/011274A1
A pulse testing method, comprising: respectively using pulses of different pulse widths to perform pulse testing on optical fibre in order to acquire test data; and fitting test data corresponding to pulses of different pulse widths. Als...  
WO/2020/008255A1
The disclosed technology relates to a process for detecting musical artifacts within a musical composition. The detection of musical artifacts is based on analyzing the energy and frequency of the digital signal of the musical compositio...  
WO/2020/010010A1
Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circu...  
WO/2020/007054A1
A shift register unit, a gate driving circuit, a driving device, and a driving method. The shift register unit comprises a first sub-shift register (100), a second sub-shift register (200), and an output control circuit (300); the first ...  
WO/2020/007059A1
A shift register unit, a driving method, a light-emission control gate driving circuit, and a display apparatus. The shift register unit comprises a light-emission control signal output end (OUT), a pull-up control node control circuit (...  
WO/2019/088820A8
The present invention generally relates to a system and method of providing audio-visual (AV) response, comprising of at least one terminal (3) capable of installing at least one AV application, said application capable of portraying AV ...  
WO/2020/010081A1
Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or mo...  
WO/2020/009735A1
In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enab...  
WO/2020/006662A1
Disclosed are a self-terminating write circuit and method for realizing self-termination of storage array circuits in different states by means of the same self-terminating write control circuit. The self-terminating write circuit of the...  
WO/2020/008496A1
The purpose of the present invention is to improve recording density with a simple configuration in the art of hologram recording. Provided is a hologram recording device for recording information by emitting signal light and reference l...  
WO/2020/007311A1
A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function ...  
WO/2020/009095A1
In order to provide a Ni-based alloy for a seed layer, the alloy enabling achievement of a seed layer that exhibits enhanced alignment to the (111) plane and that has a fine crystal grain size, a sputtering target which contains said all...  
WO/2020/000231A1
Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The...  
WO/2020/001200A1
A shift register and a driving method, a gate driving circuit and a display device. The shift register comprises: an input circuit (100), which is electrically connected to an input voltage terminal (STV) and a first clock signal termina...  
WO/2020/005856A1
Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality o...  
WO/2020/005849A1
An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit com...  
WO/2020/001603A1
The disclosure provides a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit comprises a reset circuit and a reset control circuit; the reset circuit is connected with a pull-up no...  
WO/2020/006060A1
Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in resp...  
WO/2020/002995A1
A method of depositing a metal-containing material is disclosed. The method can include use of cyclic deposition techniques, such as cyclic chemical vapor deposition and atomic layer deposition. The metal -containing material can include...  
WO/2020/005709A1
Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the...  

Matches 651 - 700 out of 861,271