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Patent Searching and Data


Matches 651 - 700 out of 855,960

Document Document Title
WO/2018/048682A1
The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre- charge circuit for pre-charging a bit line during a pre-ch...  
WO/2018/047736A1
A magneto-resistive device 100 is characterized in comprising first magneto-resistive elements 101a, 101b, a second magneto-resistive element 101c, a first port 109a, a second port 109b, a signal line 107, and a direct current input term...  
WO/2018/048607A1
Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache ent...  
WO/2018/048490A1
Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain th...  
WO/2018/045773A1
A method for updating data in a memory used for electrical compensation and a data updating apparatus, the method for updating data comprising: writing a number of a currently-updated block or a predetermined value into a nonvolatile mem...  
WO/2018/047558A1
The present invention implements a structure capable of reproducibly recording MPEG Media Transport (MMT) format data into a recording medium as BDAV or SPAV format data. The MMT format data is input via broadcast waves and so forth and ...  
WO/2018/048608A1
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another me...  
WO/2018/046075A1
According to the invention, a heat assisted magnetic recording disk drive is provided which comprises a magnetic recording medium (1) with a heat sink layer (4), characterized in that the heat sink layer (4) comprises at least a material...  
WO/2018/046682A1
The present invention relates to a device (100) for selecting a storage cell (310), the device comprising a first electrode (1), a second electrode (2) and an oxide layer (3) disposed between the first electrode and the second electrode,...  
WO/2018/047035A1
A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is ...  
WO/2018/048576A1
A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tra...  
WO/2018/046693A1
An apparatus for managing the storage of image data captured by a plurality of image capturing means is provided. The apparatus comprises designation means configured to receive a designation of the importance of at least one of the plur...  
WO/2018/042511A1
Provided is a method for resmoothing a magnetic disk to retrieve data recorded on a damaged data disk. The method comprises: a determination step for determining the height of a bulge around the damaged surface of the magnetic disk; a gr...  
WO/2018/044510A1
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further inclu...  
WO/2018/040576A1
A video editing method, device, terminal, and computer storage medium. The editing method comprises: determining a location to be edited corresponding to an audio to be edited (S101); acquiring an adjusted audio corresponding to the loca...  
WO/2018/041885A1
The invention relates to a device for controlling the refresh cycles of data stored in a non-volatile memory. The device comprises a temperature sensor capable of measuring the temperature of at least one non-volatile memory and of deliv...  
WO/2018/044755A1
Fuse state sensing circuits, devices and methods. In some embodiments, a fuse state sensing circuit can include an enable block configured to enable a flow of a fuse current resulting from a supply voltage to a fuse element upon receipt ...  
WO/2018/044487A8
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell p...  
WO/2018/043593A1
Provided is a photosensitive composition for hologram recording, with which it is possible to further improve diffraction properties. The composition includes at least: two or more types of phopolymerizable monomers; a photopolymerizatio...  
WO/2018/042285A1
To provide a novel semiconductor device or display device. The semiconductor device includes a decoder circuit, an amplifier circuit, and an arithmetic circuit. The amplifier circuit includes a first amplifier and a second amplifier. One...  
WO/2018/044486A1
Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The ...  
WO/2018/044562A2
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/043680A1
Provided is a sputtering target which enables decrease in the heat treatment temperature for ordering an Fe-Pt magnetic phase, and which is suppressed in generation of particles during the sputtering. A non-magnetic material-dispersed sp...  
WO/2018/044487A1
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell p...  
WO/2018/044485A1
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two...  
WO/2018/044562A3
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/044368A1
Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells 200 comprises a plurality of word lines 260, 262, 264, 266, 506, 508, 510. A controller...  
WO/2018/044329A1
Systems, methods, and non-transitory computer-readable media can acquire a first selection to identify a subset of media content items out of a set of media content items. A second selection to identify a mood out of a set of moods can b...  
WO/2018/044391A1
First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the...  
WO/2018/044479A1
A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transisto...  
WO/2018/042175A1
Systems and methods for superimposing the human elements of video generated by computing devices, wherein a first user device (20) and second user device (20) capture and transmit video (212, 214) to a central server (30) which analyzes ...  
WO/2018/043903A1
Disclosed are a transmitter which requires only a low cost and a small area and can eliminate switching noise, and a data transmission method therefor. The transmitter comprises: an encoder for converting two-level input data (1 and 0) i...  
WO/2018/044815A1
A ferroelectric memory and a method for operating a ferroelectric memory are disclosed. The ferroelectric memory includes a ferroelectric memory cell having a ferroelectric capacitor characterized by a maximum remanent charge, Qmax. A wr...  
WO/2018/040711A1
A shift register and a driving method thereof, a gate driving circuit and a display device. The shift register comprises: an input unit (11), configured to provide an input signal to a first node (N1); a pull-up unit (12), configured to ...  
WO/2018/043425A1
A semiconductor device having a plurality of memory cells (MC1, MC2), the semiconductor device being such that each of the plurality of memory cells (MC1, MC2) respectively has: a memory transistor (10M) having an oxide semiconductor lay...  
WO/2018/044384A1
A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of D...  
WO/2018/041557A1
A differential gain-stage circuit (10) comprises a positive and a negative input terminal (25, 26), a first capacitor (11) with a first and a second electrode (12, 13), a second capacitor (14) with a first and a second electrode (15, 16)...  
WO/2018/044503A1
The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances ...  
WO/2018/044458A1
Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells...  
WO/2018/040969A1
The present invention relates to the technical field of flash memory, and provides a method and device for improving reliability of a NAND flash memory. The method comprises the following steps: upon receiving an interrupt signal, a NAND...  
WO/2018/042814A1
The present invention makes it possible to obtain a highly accurate signal quality assessment value capable of having a high correlation with the error rate for a reproduction signal from a high-density recording medium. For this purpose...  
WO/2018/045214A1
In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibratio...  
WO/2018/044567A1
Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds,...  
WO/2018/038802A2
Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memo...  
WO/2018/038783A1
Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND str...  
WO/2018/038802A3
Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memo...  
WO/2018/037155A1
An apparatus configured to, in respect of a video provided to a user and wherein a plurality of comments are displayed such that they scroll across the video, based on the comments and one or more comment filtering rules, provide for com...  
WO/2018/037777A1
This magnetoresistive element 10 is obtained by laminating a lower electrode 31, a first base layer 21A formed of a non-magnetic material, a storage layer 22 having perpendicular magnetic anisotropy, an intermediate layer 23, a magnetiza...  
WO/2018/039059A1
A computer-implemented method is described for automatically digitally transforming and editing video files to produce a finished video presentation. The method includes the steps of recording or receiving from a user a master video, rec...  
WO/2018/038849A1
A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells includes a perpendicular magnetic tunnel junction (pMTJ) -a magnetic tunnel junction with perpendicular anisotropy- including a ...  

Matches 651 - 700 out of 855,960