| Document |
Document Title |
|
WO/2023/142187A1 |
A GOA circuit and a display panel. An inverted control module (400) of each stage of a GOA unit enables, under the control of a clock signal (CK(n+1)), potentials of a first node (Q) and a second node (QB) to be opposite, such that a dir...
|
|
WO/2023/146520A1 |
An address-skipping trim search performed by a memory built-in self-test system comprises: perform memory read operations on one memory bank to determine whether it fails to correctly sense values of stored data based on a reference trim...
|
|
WO/2023/142043A1 |
A display substrate and a manufacturing method therefor, and a display device. The display substrate (1) comprises a gate driving circuit (130) and a plurality of clock signal lines (140). The gate driving circuit (130) comprises a plura...
|
|
WO/2023/144509A1 |
Apparatus for controllably storing and releasing photons An apparatus is disclosed herein. The apparatus comprises a non-linear photonic element for outputting a signal and idler photon pair. The apparatus further comprises a module conf...
|
|
WO/2023/141992A1 |
Provided in the embodiments of the present disclosure are a memory and a control method therefor. The memory comprises: a storage array which comprises a plurality of storage surfaces, each storage surface comprising storage blocks consi...
|
|
WO/2023/142220A1 |
Embodiments of the present disclosure provide a semiconductor device layout structure and a manufacturing method therefor. The semiconductor device layout structure comprises: an active area layout layer comprising first active area patt...
|
|
WO/2023/146907A1 |
Provided is an integrated circuit comprising: an amplifier; a sensor electrically connected to a first input of the amplifier; and a set of weights electrically connected to a second input of the amplifier, wherein the amplifier is confi...
|
|
WO/2023/142206A1 |
The present disclosure relates to the field of semiconductor circuit design, in particular, to an amplification circuit, a control method, and a memory. The amplification circuit comprises: a sensing amplification circuit (101) which com...
|
|
WO/2023/142575A1 |
The embodiments of the present application relate to the field of circuits. Disclosed are a power switch circuit and an EFUSE,, which can alleviate the problem of mistaken programming caused by the fact that a Core transistor in an EFUSE...
|
|
WO/2023/141113A2 |
Examples of a head stack assembly arm are described herein. The head stack assembly arm includes a load beam in an upper nesting configuration including a lift tab with an inner edge. The head stack assembly arm includes a load beam in a...
|
|
WO/2023/138219A1 |
A memory, a timing control method, and an electronic device, relating to the technical field of storage. The memory is used for replacing a traditional DRAM, and is compatible with control instructions of the DRAM, thereby improving the ...
|
|
WO/2023/137642A1 |
The embodiments of the present disclosure relate to a ferroelectric memory and a manufacturing method therefor. The ferroelectric memory comprises a first electrode in a fin form, wherein the first electrode extends in a first horizontal...
|
|
WO/2023/140880A1 |
To increase the speed of programming of a multi-plane non-volatile memory, it is proposed to accelerate the programming of the last one or more data states for one or more slow planes.
|
|
WO/2023/137647A1 |
A method of data protection for a NAND memory includes programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and ...
|
|
WO/2023/137557A1 |
A computer implemented system is described in various embodiments herein, the system includes a processor, a memory coupled to the processor and storing processor-executable instructions that, when executed, configure the processor to: r...
|
|
WO/2023/137576A1 |
A method for debugging of flash memory devices using NAND self-verification, comprising: programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a pluralit...
|
|
WO/2023/137845A1 |
A test method for a storage chip, a test apparatus for a storage chip, and a computer readable storage medium and an electronic device, which belong to the technical field of semiconductors. The method comprises: on the basis of a target...
|
|
WO/2023/141013A1 |
An example device (100) includes: converter circuitry (104 A) having an output configured to couple to a first memory circuit (106 A) from a plurality of memory circuits (106A, 106B, 106C), the converter circuitry (104 A) configured to: ...
|
|
WO/2023/137855A1 |
Embodiments of the present application provide a test method for a memory chip and a device. The method comprises: writing test data into memory cells of a memory chip to be tested; reading stored data from the memory cells; and generati...
|
|
WO/2023/141389A1 |
he present disclosure provides systems, apparatus, methods, and computerreadable media that support linking paused video recordings captured over a period of time. In a first aspect, a method of image processing may include determining a...
|
|
WO/2023/138850A1 |
A magnetic recording tape comprises a tape substrate, a perpendicular magnetic recording layer disposed over the tape substrate, and a soft-magnetic underlayer disposed between the recording layer and the tape substrate. The perpendicula...
|
|
WO/2023/134002A1 |
A memory detection method and apparatus, and a detection simulation method. The method comprises: writing, by means of a sense amplifier, first data to a storage unit to be detected; writing second data different from the first data into...
|
|
WO/2023/133992A1 |
The present invention relates to the field of semiconductor circuit design, and in particular to a refresh circuit and a memory. The refresh circuit comprises: a preprocessing module (101) for receiving a word line enabling command and a...
|
|
WO/2023/134001A1 |
Embodiments of the present disclosure provide a clock circuit, a clock alignment system and a clock alignment method. The clock circuit comprises a signal receiving end, an equalization circuit and an analog test circuit. The signal rece...
|
|
WO/2023/133753A1 |
Provided in the present disclosure are a driving circuit, a driving method and a display apparatus. The driving circuit comprises scanning driving circuits at a plurality of stages and pixel driving circuit in a plurality of rows, wherei...
|
|
WO/2023/136242A1 |
Provided are a magnetic disk substrate having a pair of front and back main surfaces, wherein each of the front and back main surfaces has a fixing site which is brought into contact with a fixing jig when the magnetic disk substrate mad...
|
|
WO/2023/134009A1 |
The present disclosure provides a readout circuit architecture and a sense amplification circuit, comprising: a readout amplification unit, comprising a first P-type transistor and a second P-type transistor; a first offset compensation ...
|
|
WO/2023/134297A1 |
A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2 (N-M) th memory state; when the program verificatio...
|
|
WO/2023/133975A1 |
A readout circuit layout, comprising: a first PMOS layout used for forming a first PMOS tube , a source of the first PMOS tube being connected to a first signal end, and the first signal end being used for receiving a first level signal;...
|
|
WO/2023/133877A1 |
A method of data protection for a NAND memory includes programming first and second pages of a NAND flash memory device according to programming data such that data stored in the first and second pages are redundant. The programming of t...
|
|
WO/2023/134138A1 |
A sensitivity amplifier and a driving method therefor, and a memory. The sensitivity amplifier comprises an amplification circuit and a voltage equalization circuit, wherein the amplification circuit comprises a first P-type transistor, ...
|
|
WO/2023/135739A1 |
According to an embodiment of the present invention, a semiconductor storage device comprises: a non-volatile memory cell; a sensing circuit that senses a first voltage and selects one of a first mode and a second mode on the basis of th...
|
|
WO/2023/134005A1 |
Disclosed in embodiments of the present disclosure are a semiconductor structure and a forming method therefor. The semiconductor structure comprises: a substrate; an integrated circuit device layer, the integrated circuit device layer b...
|
|
WO/2023/134299A1 |
A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N-1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to: in the pr...
|
|
WO/2023/133967A1 |
Provided is an antifuse memory; an inverting input end of an operational amplifier is connected to a feedback end of a bias voltage generation module; a voltage of a second input end can be obtained according to a voltage of the feedback...
|
|
WO/2023/136925A1 |
Latch array with mask-write functionality including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a fi...
|
|
WO/2023/133973A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular to a local amplification circuit, a data readout method, and a memory. The local amplification circuit comprises: a write control transistor (...
|
|
WO/2023/134023A1 |
Embodiments of the present disclosure provide an inductive amplifier circuit, a method, and a semiconductor memory. The inductive amplifier circuit comprises: a transmission circuit for receiving a signal to be processed, performing tran...
|
|
WO/2023/133776A1 |
Embodiments of the present application provide a magnetic storage unit, a memory, and a manufacturing method. The magnetic storage unit comprises: an electrode layer; a magnetic tunnel junction disposed on the electrode layer, the magnet...
|
|
WO/2023/133974A1 |
The present invention relates to the field of semiconductor circuit design, and in particular to a local amplification circuit, a data read-out method, and a memory. The local amplification circuit comprises: write control transistors (1...
|
|
WO/2023/135019A1 |
The invention relates to a magneto resistive memory de device (100) comprising a memory array (10) comprising at least one bit line (BL) and at least one source line (SL, SLB), the bit line (BL) and the at least one source line (SL, SLB)...
|
|
WO/2023/133952A1 |
The present disclosure provides a memory structure and a storage system. The memory structure has an array structure, comprising: a storage controller and a plurality of memories; at least one storage redistribution layer is provided on ...
|
|
WO/2023/136853A1 |
A data storage device has a closed loop extended park mode during spin down operation. A data storage device comprises a spindle motor configured to rotate one or more disks, and one or more processing devices. The one or more processing...
|
|
WO/2023/133774A1 |
Embodiments of the present application provide a magnetic memory cell and a manufacturing method therefor. The magnetic memory cell comprises a magnetic tunnel junction and an electrode layer. The magnetic tunnel junction comprises a fre...
|
|
WO/2023/130578A1 |
A testing method and a testing apparatus for a memory. The method comprises: after at least one word line is activated, executing a reading operation at least twice on a memory unit to be tested, said memory unit being connected to the a...
|
|
WO/2023/130487A1 |
Provided in at least one embodiment of the present disclosure are a data processing method based on a memristor array, and an electronic apparatus. The data processing method based on a memristor array comprises: acquiring a plurality of...
|
|
WO/2023/132855A1 |
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store a plurality of codewords in the memory device. Each codeword of the plurality of codewords includes host ...
|
|
WO/2023/130582A1 |
Provided in the present disclosure is a data extraction circuit. The data extraction circuit comprises: a first input circuit, wherein an input end of the first input circuit establishes first input data under the triggering of a first d...
|
|
WO/2023/132857A1 |
A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is confi...
|
|
WO/2023/133237A1 |
A video is generated from an audio file by transcribing the audio file into texts and breaking the audio file into one or more segments or shots used as scenes. A media piece is then matched to each shot; the media pieces are properly co...
|
