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Patent Searching and Data


Matches 701 - 750 out of 844,814

Document Document Title
WO/2016/092676A1
Provided is a storage device that achieves a reduction in error rate at the time of data write and data erasure in the storage device to thereby enable high-speed data reading and writing. The storage device is provided with a controller...  
WO/2016/093996A1
Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparat...  
WO/2016/090515A1
The invention relates to a high-density magnetic storage medium provided with low-symmetry ferromagnetic particles, wherein said particles are formed by segments or bars, or systems of bars and combinations of said bars which form struct...  
WO/2016/089574A1
Static random access memory (SRAM) bit cells with wordline landing pads (312(1), 312(2), 312(3)) are split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline (...  
WO/2016/086430A1
A processing machine of display device, the processing machine comprising: a metal support plate (12); a plurality of supporting structures (13) movably disposed on the metal support plate, for supporting on a non-display area of the gla...  
WO/2016/089474A1
Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells con...  
WO/2016/090353A3
In described examples of systems and methods for load current compensation for analog input buffers, an input buffer (300) may include: a first transistor (Q1) having a collector terminal coupled to a power supply node and a base termina...  
WO/2016/089563A1
Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can ...  
WO/2016/089467A1
Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and era...  
WO/2016/087763A1
The invention relates to a circuit for reading a programmed resistive state of resistive elements (102) of a resistive memory (101), wherein each resistive element may be programmed to be in a first or a second resistive state (Rmax, Rmi...  
WO/2016/086714A1
Disclosed are a recording apparatus and a terminal. The recording apparatus comprises: a microphone arranged on a PCB, and a microphone interface. The microphone interface extends outwards at one side of a housing, and the microphone is ...  
WO/2016/089603A1
An STT magnetic memory includes adjacent columns of STT magnetic memory elements having a top electrode and a bottom electrode. A shared bit line is coupled to the top electrode of the STT magnetic memory elements in at least two of the ...  
WO/2016/090133A1
A system and method for producing a new globally -unique identifier (GUID) format that may be used, for instance, to uniquely identify a number of different items in a distributed computer system, such as, for example, transactions in an...  
WO/2016/089241A1
´╗┐The present invention relates to a writing method, a reading method and a shingled recording system for shingled magnetic recording principle for a hard disk drive comprising multiple tracks, wherein the written bits of one byte are a...  
WO/2016/086566A1
A shift register unit, a driving method therefor, a gate drive circuit, and a display device. The shift register unit comprises a latch module (10) and a latch output module (20). Instead of a clock signal, an intermediate signal generat...  
WO/2016/088448A1
The present invention suppresses memory cell degradation in nonvolatile memory. A memory controller is provided with a timer unit, elapsed time determination unit, and reading unit. The timer unit times the elapsed time that has passed s...  
WO/2016/086431A1
A liquid-crystal display device and a shift register thereof are provided. Each shift register unit of the shift register comprises a storage circuit (31), an electric potential control circuit (32) and a phase-inverter circuit (33), whe...  
WO/2016/088741A1
Disclosed is a method for reducing the time from re-activation of a power supply following disconnection of the power supply to the start of recording in a constantly operating video recording apparatus. The recording apparatus is provid...  
WO/2016/087583A1
Methods and devices are described for reducing the audible effect of pre- responses in an audio signal. The pre-responses are effectively delayed by employing a digital non-minimum-phase filter, which includes a zero lying outside the un...  
WO/2016/089587A1
Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read w...  
WO/2016/089646A3
Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a si...  
WO/2016/088298A1
The record playback apparatus of the present disclosure is provided with: a plurality of optical pickups for recording information on a recording medium or playing back information from the recording medium; a single transport mechanism ...  
WO/2016/085470A1
A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-pol...  
WO/2016/082340A1
A charging scanning and charge sharing scanning dual-output GOA circuit, combining a timing with a circuit; an nth stage GOA unit circuit receives a first low frequency clock signal (LC1), a second low frequency clock signal (LC2), a dir...  
WO/2016/085845A1
A storage device includes a controller that implements an interlaced magnetic recording scheme with prioritized random access. According to one implementation, a controller is configured to write data at a first linear density to alterna...  
WO/2016/084138A1
A laser irradiation device includes a laser light source L, a spatial light modulator SLM for spatially modulating the laser light from the laser light source, and an optical system OP for focusing the laser light onto an irradiation obj...  
WO/2016/084497A1
The present invention suppresses memory cell degradation in nonvolatile memory. A read processing unit carries out read processing in which reading data is read from a plurality of memory cells on the basis of a first threshold. An error...  
WO/2016/085629A1
A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing, at the comparison circuit, a first resistance of the first MTJ element to a s...  
WO/2016/082141A1
A block memory configuration structure and configuration method, the block memory configuration structure comprising: a first port, a second port, an ECC module, an FIFO module; the first port has write width and read width of different ...  
WO/2016/083865A1
Provided is a semiconductor memory management method, the method comprising the following steps: on the basis of a sampling time period, sampling a row address from an access stream of a memory unit array; on the basis of probability inf...  
WO/2016/082760A1
A resistor switching circuit, a storage circuit and a consumable chip. The resistor switching circuit is used in the consumable chip, and comprises a plurality of resistor switching branch circuits, the resistor switching branch circuit ...  
WO/2016/085460A1
Examples disclosed herein relate to a switch between a first power source and a second power source. Examples include a first power source electrically coupled to a load via a first transistor and a second transistor. A second power sour...  
WO/2016/083288A1
The invention relates to an SC amplifier circuit (10) which is used to amplify an input voltage of a measurement signal source present at an input by an amplification factor and to output the amplified input voltage at an output during a...  
WO/2016/084781A1
The purpose of the present invention is to provide a fluoropolyether compound which has exceptional heat resistance and with which it is possible to maintain the lubricity of a magnetic disk surface without evaporating at high temperatur...  
WO/2016/082425A1
The present invention provides a memory detecting method and network processor, wherein the method comprises: the network processor writes a first characteristic value into the memory according to an index; the network processor reads a ...  
WO/2016/086100A1
Methods, systems, and computer readable media can be operable to facilitate the detection and management of a filler region during trickplay of a content stream. A filler region at the edge of a targeted advertisement segment may be dete...  
WO/2016/085947A1
A storage device includes a transducer head including a first write element configured to write data at a first write width and a second write element configured to write data at a second write width less than the first write width. Acco...  
WO/2016/086239A1
A storage device controller addresses consecutively-addressed portions of incoming data to consecutive data tracks on a storage medium and writes the consecutively-addressed portions to the consecutive data tracks in a non-consecutive tr...  
WO/2016/084519A1
[Problem] To provide an information processing device capable of providing users with enjoyment in taking a test, by dynamically determining the points allocation for questions. [Solution] An information processing device equipped with a...  
WO/2016/082800A1
A memory activation method and device, which relate to the field of computers. In the solutions, a first memory access request is acquired, the first memory access request being used to request to access a first sub row in memory (100); ...  
WO/2016/081158A1
An apparatus includes an array of bit cells (202, 204, 206, 208) that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line (240) configured to be selectively coupled to...  
WO/2016/079971A1
A magnetic recording medium is provided with: a flexible, long substrate; a soft magnetic layer; and a magnetic recording layer. The squareness ratio of the substrate in the longitudinal direction is equal to or less than the squareness ...  
WO/2016/079925A1
A play list file for controlling the playback of a VOB stream file is recorded on a recording medium. CombiExt_for_Cell () and Combi () representing a combination of elementary streams that can be played back simultaneously in an identic...  
WO/2016/081061A1
Erasing blocks of a nonvolatile memory may include two erase steps. A first erase step brings the memory cells of a block to an intermediate state between their programmed states and an erased state. The block is then maintained with the...  
WO/2016/080146A1
This semiconductor device is provided with: a flip flop circuit which has an annular structure wherein a first inverter circuit, a first connection line comprising a first node, a second inverter circuit, and a second connection line com...  
WO/2016/081304A1
Various systems and methods for automated audio adjustment are described herein. A processing system for automated audio adjustment may include a monitoring module to obtain contextual data of a listening environment; a user profile modu...  
WO/2016/081064A1
Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or...  
WO/2016/079358A1
The invention relates to a system that permits the automatic detection of a traffic offence caused by a vehicle in an application zone of the system. To that end, the system is implemented by means of an autonomous capturing unit (UCA) t...  
WO/2016/079085A1
A VCMA memory element comprises a first magnetic stack comprising a first gate dielectric layer (201) sandwiched in between a first gate electrode (101) and a first free ferromagnetic layer (701) and a second magnetic stack comprising a ...  
WO/2016/081190A1
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and addr...  

Matches 701 - 750 out of 844,814