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Matches 701 - 750 out of 850,999

Document Document Title
WO/2016/172636A1
A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and ...  
WO/2016/170714A1
This HDD holding device 10 comprises a base part 11, a plurality of shock-absorbing members, and an HDD mounting part 12 on which an HDD 60 is mounted. The plurality of shock-absorbing members include: a shock-absorbing member 13y which ...  
WO/2016/171819A1
A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail ad...  
WO/2016/171788A1
In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bi...  
WO/2016/170527A1
A recording medium is provided, such as paper, secured by magnetic microwires. The recording medium comprises: a pulp structure formed by pulp fibers, said pulp structure carrying microwires having a metal core of a predetermined materia...  
WO/2016/170885A1
 A magnetic sensor device which is capable of determining whether a magnetic pattern applied to a medium is a hard magnetic material or a soft magnetic material is provided. Specifically, the magnetic sensor device 20 is provided with ...  
WO/2016/171875A1
An active three-terminal superconducting device having an intersection region at which a hot spot may be controllably formed is described. The intersection region may exhibit current crowding in response to imbalances in current densitie...  
WO/2016/170905A1
A content playback device (1) includes: a first non-volatile memory (120); a second non-volatile memory (121); a read unit (2) that reads out content data recorded in removable media; and a management unit (3) that writes media managemen...  
WO/2016/167821A1
A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a p...  
WO/2016/167862A1
Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic ...  
WO/2016/167785A1
Example implementations relate to determining resistive state of memristors in a crossbar memory. For example, a method includes biasing each row of memristors and each column of memristors of the crossbar memory with a first voltage, an...  
WO/2016/166266A1
A method and a device are provided in order to speed up the production and to improve the quality of volume holograms (200) in a photopolymer material (310). The claimed method comprises exposing the photopolymer material (310) with an e...  
WO/2016/166838A1
The present invention pertains to a playback device, a playback method, and a program with which it is possible to transmit, to a display device, information about the color gamut and the dynamic range of brightness of content stored in ...  
WO/2016/168602A3
A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular r...  
WO/2016/167082A1
A configuration is provided for acquiring image information of multiple image data to be applied to ultra-high-definition (UHD) image playback, and enabling image playback to which the multiple image data is applied. Image information of...  
WO/2016/167911A1
A bit line and word line tracking circuit is provided that accounts for the power-supply-voltage-dependent delays in a memory having a logic power domain powered by a logic power supply voltage and a memory power domain powered by a memo...  
WO/2016/166639A1
A logic gate module (10) for performing logic functions comprising a MRAM cell (1) including a magnetic tunnel junction (2) comprising a sense layer (21), a storage layer (23), and a spacer layer (22), the MRAM cell (1) having a junction...  
WO/2016/165346A1
A method and apparatus for storing and playing an audio file. The method includes: dividing the audio file into independent continuous voice segments; for each continuous voice segment, determining the identification information of a spe...  
WO/2016/167971A1
Hard disk drives of the invention are wrapped in wraps for enhanced sealing of the hard disk drive. Wrapped hard disk drives of the invention comprise: an enclosed hard disk drive housing comprising a base and a cover enclosed around int...  
WO/2016/167778A1
In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multipli...  
WO/2016/168238A1
Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional i...  
WO/2016/168832A1
Content is transferred from a first non-volatile storage medium to a second non-volatile storage medium without reproduction. This is accomplished by reading first data stored in the first non-volatile storage medium from the first non-v...  
WO/2016/168123A1
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N- well and an anti-fuse cell formed on the N- well. The anti-fuse cell includes a drain P+ diffusion deposited in the N- well, a source P+ diffusion deposited i...  
WO/2016/165546A1
Provided are a shift register and a unit thereof. A low-level maintaining module (30) comprises a first maintaining unit (31) and a second maintaining unit (32). The first maintaining unit (31) and the second maintaining unit (32) are re...  
WO/2016/166931A1
Provided is a magnetic recording medium comprising: a support; a base layer containing a carbon particle powder and a metal-containing particle powder; and a recording layer. At the recording surface, the maximum indentation depth h is 8...  
WO/2016/167869A1
A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic MgO-comprising material over conductive material of the magnetic electrode being formed. An amorphous metal is formed over the MgO-comp...  
WO/2016/168602A2
A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular r...  
WO/2016/167756A1
One example includes a resistive random access memory (RRAM) system. The system includes a resistive memory element to store a binary state based on a resistance of the resistive memory element. The system also includes an RRAM write cir...  
WO/2016/165393A1
A hard disk installation device, comprising: an installation box and at least one installation case configured to install a hard disk, wherein the installation box is provided with a fixing part, and the installation case is detachably f...  
WO/2016/168695A1
Power rail control systems that include power multiplexing circuits that include cross-current conduction protection are disclosed. Power multiplexing circuit includes supply selection circuits each coupled between a respective supply po...  
WO/2016/166980A1
An actuator 100 comprising: a holder 50 having a rotation shaft 52, and a mounting surface to which a diffraction grating 1 is attached; a fixed part 20 having a bearing 21a that holds the rotation shaft 52 of the holder 50; an elastic m...  
WO/2016/161865A1
A hard disk installation device comprises a container (101) and a cover (102) matching the container (101). A hard disk (104) is fixed by the container (101) and the cover (102), and the container (101) and the cover (102) are fixed by a...  
WO/2016/163312A1
Provided are an optical information recording and reproduction device capable of generating a control signal with suitable signal quality even when the light quantity of a reproduction signal fluctuates in a holographic memory, and a met...  
WO/2016/161768A1
A shift register unit (100 and 300), a gate driver circuit, a display device (800), and a driving method for use in the shift register unit (100 and 300). The shift register unit (100 and 300) comprises: an input module (10), which contr...  
WO/2016/164049A1
A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compens...  
WO/2016/162560A1
The invention relates to a method for detecting and synchronizing audio/video signals. At least one audio signal (140) is detected by means of at least one microphone unit (110). Timestamps (117) are generated and stored together with th...  
WO/2016/164319A1
A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to prog...  
WO/2016/164779A1
In some embodiments, systems and methods for storing and/or retrieving digital information in a nucleic acid library are provided. In some embodiments, an integrated system comprising a nucleic acid synthesis device, a nucleic acid seque...  
WO/2016/163100A1
This video server is provided with: a plurality of ports used for input and output of source data; a storage unit capable of storing group information relating to grouping of the plurality of ports; and a control unit which receives a sp...  
WO/2016/161626A1
Disclosed in the embodiments of the present invention are a storage device and unmanned aircraft employing the same. The storage device comprises: a solid-state hard disk, configured to store data; an mSATA connector, electrically connec...  
WO/2016/161901A1
A shift register adaptable to a negative threshold voltage and unit thereof. The shift register comprises a plurality of cascaded shift register units. The shift register units comprise: a charging module (11), a driving module (12), a d...  
WO/2016/163978A1
A memory cell includes either a nonvolatile resistance memory device or a nonvolatile memory device in series with a selector. The nonvolatile resistance memory device includes a dielectric layer sandwiched between a first bottom electro...  
WO/2016/164229A1
The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.  
WO/2016/164270A1
An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve better performance characteristics and read stability without a multistage opera...  
WO/2016/161726A1
A shift register unit comprising a pull-up module (101), an input module (102), a pull-down control module (103), a pull-down module (104), a reset and discharge module (105), a voltage divider module (106), a holding module (107), and a...  
WO/2016/161725A1
A shift register unit (100) comprising a pull-up module (101), an input module (102), a reset module (103), a first pull-down module (104), a second pull-down module (105), a first control module (106), a second control module (107), a f...  
WO/2016/161727A1
Provided are a shift register unit, a driving method, an array substrate gate electrode driver device, and a display panel, for use in reducing the duty cycle of a thin-film transistor connected at a pull-down node, thus preventing aging...  
WO/2016/158867A1
This magnetoresistive effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer sandwiched between the first and second ferromagnetic metal layers, wherein: the tunnel barrier la...  
WO/2016/160165A1
Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level ...  
WO/2016/160950A1
An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the mem...  

Matches 701 - 750 out of 850,999