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WO/2023/171474A1 |
A memory controller according to an embodiment of the present disclosure is capable of controlling access to a DRAM. The memory controller comprises an RAA counter capable of counting the number of issuances of an ACT command and a comma...
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WO/2023/164911A1 |
Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact cou...
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WO/2023/167805A1 |
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. I...
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WO/2023/165058A1 |
The present disclosure provides a method and apparatus for implementing mirror image storage of a memory model, and a storage medium, and relates to artificial intelligence chips, intelligent voice, and other artificial intelligence fiel...
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WO/2023/164827A1 |
The present disclosure provides an SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a firs...
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WO/2023/166376A1 |
Provided is a novel semiconductor device. In this semiconductor device, a first circuit is electrically connected to a second circuit via a first wire; the first circuit is electrically connected to a fourth circuit via a third wire and ...
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WO/2023/165981A1 |
According to various aspects, a memristive crossbar array is provided including: first control lines and second control lines in a crossbar configuration defining a plurality of cross-point regions, a memristive material portion disposed...
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WO/2023/165002A1 |
The present disclosure relates to the field of semiconductor circuit design, in particular to a data writing circuit, a data writing method, and a memory. The data writing circuit comprises: a delay generation module, for generating, on ...
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WO/2023/167244A1 |
The present invention utilizes an electric characteristic due to an electrochemical reaction corresponding to an environmental factor. An interconnection structure according to an embodiment of the present disclosure electrically connect...
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WO/2023/167681A1 |
A memory-testing circuit in a circuit comprises: a test controller; a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an o...
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WO/2023/165440A1 |
The present disclosure provides a programming method, a memory device and a memory system. The method includes, based on coupling offsets, dividing target programmed states into N groups, each group corresponding to a different first pro...
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WO/2023/165014A1 |
Provided in the present application are a programmable circuit, an integrated circuit and an electronic device. The programmable circuit comprises: a signal conversion module, which converts a parallel signal input by an external circuit...
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WO/2023/165729A1 |
A memory and routing module (100) includes a substrate (170) and a connection component (160). The connection component (160) is attached to the substrate (170) and includes multiple pins (161) that connect the module (100) to a correspo...
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WO/2023/168085A1 |
Technologies include systems, devices, and methods to write, store, read, and perform computation of digital information using nucleic acid molecules (e.g., DNA). The technologies include, for example, a device including one or more indi...
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WO/2023/165003A1 |
The present disclosure relates to the field of semiconductor circuit design, and relates in particular to a data readout circuit, a data readout method and a memory. The method comprises: a delay generation module generates, on the basis...
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WO/2023/165026A1 |
Embodiments of the present invention provide a refresh circuit, a memory, and a refreshing method. The refresh circuit comprises: a refresh counter, configured to output an address signal by means of a plurality of address pins; an addre...
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WO/2023/166138A1 |
An image processing device is provided. The image processing device includes interface circuitry configured to receive first image data representing a first image exhibiting a first aspect ratio smaller than one. The first image is a pho...
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WO/2023/167115A1 |
In modern computing, the reference for calculating storage capacity is bits, the number of transistors (elements) that become a node, namely, the number of bits is a unit of a modern information communication quantity. On the contrary, a...
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WO/2023/167728A1 |
A computing device is provided. The computing device may include a first camera configured to capture a primary image sequence of a scene, and a second camera configured to substantially concurrently capture a secondary image sequence of...
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WO/2023/165044A1 |
Provided in the present disclosure are a memory detection method, circuit, apparatus and device, and a storage medium. The memory detection method comprises: writing test data into at least some storage units of a memory; turning on word...
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WO/2023/165934A1 |
Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage d...
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WO/2023/162804A1 |
A memory device according to one aspect of the present disclosure comprises a nonvolatile memory cell array unit, and a memory controller that controls a writing operation and reading operation with respect to the nonvolatile memory cell...
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WO/2023/159968A1 |
Provided in the present invention are a non-volatile memory and a programming method therefor, and a computer system. The programming method for a non-volatile memory comprises: a programming step of applying a programming pulse to a sto...
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WO/2023/163731A1 |
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The wo...
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WO/2023/163730A1 |
A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a sub...
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WO/2023/159714A1 |
The present disclosure relates to the technical field of semiconductors. Provided is a detection method for a leakage current of a memory. The detection method comprises: providing a memory array, wherein the memory array comprises a plu...
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WO/2023/159680A1 |
A testing method, a computer device, and a computer-readable storage medium, by means of which an effective test can be performed for the expiration of a write recovery time. The testing method comprises: writing first data into a target...
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WO/2023/163959A1 |
Examples of a suspension are provided. The suspension includes a mount plate attached to a load beam at a suspension assembly attachment point. The suspension may include a first actuator and a second actuator located at the mount plate....
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WO/2023/163735A1 |
Described herein are sliders and data storage devices that promote particle mobility to improve particle robustness. In some embodiments, a data storage device includes a recording medium and a slider. A surface of the slider air-bearing...
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WO/2023/162632A1 |
A neural network computation circuit comprising a plurality of word lines (501), a memory cell (600), a word line drive circuit (503), a column selection circuit (504), computation circuits (5051-505n) for carrying out a neuron computati...
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WO/2023/163738A1 |
Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuator assembly comprising a head, and configured to position the head over a corresponding disk surface; and one or more processing ...
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WO/2023/159667A1 |
A method for enhancing electric leakage between adjacent memory cells, and an electric leakage detection method and apparatus. The method for enhancing electric leakage between adjacent memory cells comprises: performing a write operatio...
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WO/2023/161755A1 |
Provided is a storage device that includes a novel semiconductor device. The storage device comprises: a memory cell that includes a transistor and a capacitive element; and a conductor. The transistor includes one of a source electrode ...
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WO/2023/161757A1 |
Provided is a semiconductor device that enables miniaturization and high integration. The semiconductor device has: a first transistor that includes a first conductor, a first insulator, a first metal oxide, a second insulator, and a sec...
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WO/2023/159734A1 |
The present disclosure relates to a data transmission circuit, a data transmission method, and a memory. The data transmission circuit comprises: at least two data transmission structures, wherein each data transmission structure compris...
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WO/2023/164496A1 |
Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT ...
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WO/2023/163736A1 |
Disclosed herein are sliders with deep holes, data storage devices including such sliders, and methods of manufacturing such sliders. The holes can be situated near the edges of the slider to improve the stability and/or damping of the s...
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WO/2023/163815A1 |
Manufacturing yield loss of NAND Flash dies is reduced by selecting a plane to store a read-only reserved block and another plane to store a backup read-only reserved block based on the Number of Valid Blocks (NVB) blocks in each plane i...
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WO/2023/163733A1 |
A multiple-actuator hard disk drive includes a first actuator associated with a first logical unit and configured to operate on a first set of disk surfaces, a second actuator associated with a second logical unit and configured to opera...
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WO/2023/163737A1 |
Disclosed herein are sliders with at least one notch-cut in the trailing pad, methods of making them, and data storage devices comprising them. In some embodiments, a slider comprises a leading-edge surface, a trailing-edge surface, and ...
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WO/2023/162927A1 |
A storage device (1) according to one embodiment of the present disclosure is provided with: a storage element and a reference element each including a fixation layer having a fixed magnetization direction, a storage layer having a chang...
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WO/2023/159736A1 |
A data error correction circuit and a data transmission circuit. The data error correction circuit comprises: a decoding module (21), an input end of which is connected to a data bus, wherein the decoding module is used for receiving fir...
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WO/2023/163978A1 |
A hard disk drive (HDD) includes a suspension connected to a stack arm. The suspension includes a mount plate, a hinge, a load beam, and a circuit. The mount plate includes a bottom surface facing a disk and an ear portion extending from...
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WO/2023/159803A1 |
A read-write conversion circuit and a memory. The read-write conversion circuit is connected to a global signal line, is connected to a sense amplifier array by means of a local signal line and a complementary local signal line, and is u...
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WO/2023/159733A1 |
The present disclosure relates to a memory circuit, a data transmission circuit, and a memory. The memory circuit comprises: at least one memory structure provided in parallel to a data transmission area, each memory structure comprising...
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WO/2023/156482A1 |
The invention relates to a photopolymer composition comprising a) matrix polymers, b) writing monomers, c) at least one photoinitiator system, d) optionally at least one non-photopolymerisable component, e) optionally catalysts, radical ...
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WO/2023/156882A1 |
Provided is a highly reliable storage device. Among an information bit and a check bit constituting a humming code, the information bit having a longer bit length than the check bit is stored in a first storage unit, and the check bit is...
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WO/2023/155284A1 |
A test method for a memory chip and a device therefor. The method comprises: writing test data into a memory cell of a memory chip to be tested, a word line turn-on voltage tested by the memory chip to be tested being greater than a stan...
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WO/2023/158938A1 |
Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i, j), each device includes a Vdd terminal, and a Vss terminal. For an embodimen...
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WO/2023/158453A1 |
Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuator assembly comprising a head, and configured to position the head over a corresponding disk surfaces; and one or more processing...
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