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Matches 701 - 750 out of 855,772

Document Document Title
WO/2018/009282A1
Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference volta...  
WO/2018/006131A1
A memristor device is provided, comprising a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electro...  
WO/2018/009298A1
A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the...  
WO/2018/008161A1
Provided is a glass substrate for a magnetic recording medium, wherein the glass substrate has a glass strain point Ts of 585°C or more, the maximum value of retardation measured by radiating light having a wavelength of 543 nm in a ver...  
WO/2018/009299A1
Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including ...  
WO/2018/009302A8
A memory and a method for operating the memory are presented. The memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cel...  
WO/2018/009157A1
A memory including a top electrode and a bottom electrode; and an oxide layer including a plurality of intimately mixed oxides throughout the oxide layer. A memory including a top electrode and a bottom electrode; an oxygen exchange laye...  
WO/2018/009302A1
A memory and a method for operating the memory are presented. The memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cel...  
WO/2018/008946A1
The present invention relates to an analog digital interface SRAM structure wherein, by using a structure having a switch added to a bit line structure and an IO circuit of a conventional SRAM, stored digital data can be read as analog d...  
WO/2018/000945A1
A shift register unit, driving method therefor, gate driver circuit and display device, the shift register unit comprising: an input module (1), a reset module (2), a control module (3), a pull-down module (4) and an output module (5); a...  
WO/2018/004733A1
A method of generating a moving thumbnail is disclosed. The method includes sampling video frames of a video item. The method further includes determining frame-level quality scores for the sampled video frames. The method also includes ...  
WO/2018/004819A3
Techniques and mechanisms to provide a connector for securing to a first printed circuit board (PCB). In an embodiment, the connector is configured to receive a second PCB, where a first hardware interface of the connector includes condu...  
WO/2018/004617A1
In accordance with embodiments of the present disclosure, a method of neutralizing voltage kickback associated with a reference buffer of a switched capacitor based data converter having a first switched capacitor coupled to an output no...  
WO/2018/004753A1
Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interfac...  
WO/2018/004752A1
Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. In one aspect, a read pass voltage is discharged in a manner that purges...  
WO/2018/004608A1
Disclosed are magnetic tunnel junction (MTJ) devices, computing devices, and related methods. An MTJ device includes an MTJ body, an electrode, and a thermal resistor. The thermal resistor is operably coupled between the MTJ body and the...  
WO/2018/004748A1
A storage system includes a controller that is configured to make host data inaccessible. To do so, the controller may control power control circuitry to supply pulses to storage locations storing host data. The pulses may include flash ...  
WO/2018/005187A1
Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bi...  
WO/2018/004612A1
Disclosed are magnetic tunnel junction (MTJ) devices, computing devices, and related methods. An MTJ device includes an MTJ body, an electrode, and a heating region. The heating region is disposed between the MTJ body and the electrode. ...  
WO/2018/005019A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, inc...  
WO/2018/005868A1
An apparatus has a cathode target with a cathode target outer perimeter. An inner magnetic array with an inner magnetic array inner perimeter is at the cathode target outer perimeter. An outer magnetic array has an outer magnetic array o...  
WO/2018/003878A1
Provided is a method for producing a magnetic disk substrate, which is capable of reducing scratches in the substrate surface after polishing, while maintaining a high polishing rate. The present disclosure relates to a method for produc...  
WO/2018/005698A1
Systems for performing source line sensing of magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a MeRAM circuit includes a plurality of voltage controlled magnetic tunnel junction...  
WO/2018/003931A1
A TFT circuit (101) is provided with: a first node (N1) to which a first low potential (Vc) is supplied; a depression-type first TFT (21) that is disposed between the first node (N1) and a low-potential wiring (11) for supplying a second...  
WO/2018/004548A1
A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; ...  
WO/2018/005699A1
Systems and methods for performing word line pulse techniques in magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a magnetoelectric random access memory (MeRAM) circuit, includin...  
WO/2018/004698A1
Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between ...  
WO/2018/004663A1
A two transistor memory cell is described with amorphous oxide semiconductors and silicon transistors. In some examples a memory cell includes a sensing transistor having a source coupled to a read bit line and a drain coupled to a read ...  
WO/2018/004840A1
An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configu...  
WO/2018/004796A3
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a sou...  
WO/2018/004830A1
A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of...  
WO/2018/004587A1
Approaches for fabricating RRAM stacks with two-dimensional (2D) barrier layers, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect di...  
WO/2018/000517A1
A power management circuit, comprising a master control digital logic module (10), an operating mode power voltage regulator circuit (20), and a sleep mode power voltage regulator circuit (30). An operating power output end (202) of the ...  
WO/2018/004659A1
A three transistor memory cell is described with metal oxide semiconductors. The memory cell in some examples has a pass gate transistor having a source coupled to a read bit line and a gate coupled to a read word line, a sensing transis...  
WO/2018/005100A1
Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the...  
WO/2018/004648A1
Embodiments of the present disclosure describe apparatuses, methods, and systems associated with magnetoelectric cells. A magnetoelectric cell may include a magnetic tunnel junction that includes a fixed magnet layer and a free magnet la...  
WO/2018/004368A1
A technique for managing SSDs in a data storage system generates an endurance value for each of multiple SSDs and arranges the SSDs in RAID groups based at least in part on the generated endurance values. As a result of such arranging...  
WO/2018/004562A1
Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a condu...  
WO/2018/003147A1
The present invention provides a reproduction system in which behaviors of two persons can be easily compared with each other. A reproduction system (10) according to the present invention is characterized by comprising: a storage means ...  
WO/2018/004796A2
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a sou...  
WO/2018/003050A1
In the present invention, a nonvolatile memory device reads data from a read source area in a nonvolatile memory using a preset reading threshold, and corrects errors in the data. If the nonvolatile memory device fails to correct errors,...  
WO/2018/004756A1
In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also hav...  
WO/2018/005572A1
A two-dimensional accessible non-volatile memory apparatus includes an array comprising a plurality of non-volatile memory cells, the array being a crossbar-based non-volatile memory structure, the memory cells being arranged in a plural...  
WO/2018/005224A1
Systems and methods for performing an action based on viewing positions of other users are provided. Viewing progress in a media asset of each of a plurality of users is retrieved. The viewing progress of each of the plurality of users i...  
WO/2018/004574A1
Approaches for fabricating RRAM stacks with an amorphous bottom ballast layer, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disp...  
WO/2018/004377A1
The utility model relates to devices, and particularly cases, for storing and using memory devices such as USB flashdrives, memory cards and other solid-state data storage devices. The technical result of the utility model consists in th...  
WO/2018/004998A1
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communicat...  
WO/2018/005871A1
A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit desig...  
WO/2018/000237A1
Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the...  
WO/2018/006002A1
Embodiments of disk drive head suspensions are described that include a spring metal layer. The spring metal layer includes a base region, support arms extending from the base region, and a slider mounting region. The slider mounting reg...  

Matches 701 - 750 out of 855,772