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WO/2023/190146A1 |
This memory circuit (11) comprises: first switches (SW) which are provided for each group of a first bit line (BL1) and a second bit line (BL2) and are connected to a first memory cell (MC1) and a second memory cell (MC2); an all first b...
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WO/2023/183977A1 |
The present invention relates to a computer-implemented system and method for providing streams and playbacks of video and audio recordings in respect of artist performances before live audiences. In particular, the invention relates to ...
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WO/2023/187132A1 |
Disclosed is a device for recording data in nucleic acids. The device comprises a liquid dispenser configured to dispense a carrier drop, a drop collecting element, wherein during operation of the device the carrier drop flies from the l...
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WO/2023/187420A1 |
A memory including: an array of memory cells; a memory access logic programmable to generate a write allocation that maps an input comprising elements of data in a first sequence to the memory cells of the array and a read allocation tha...
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WO/2023/192964A1 |
Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be re...
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WO/2023/184705A1 |
The present disclosure provides a data transmission circuit and method, and a storage device. The data transmission circuit comprises a mode register data processing module, an external data transmission module and an internal data trans...
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WO/2023/192733A1 |
The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a near field transducer (NFT), a vertical cavity surface emitting laser (VCSEL) device, and a wavegui...
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WO/2023/189233A1 |
An object of the present invention to provide a magnetic disk that is flat while being thin, and is resistant to physical errors. The present invention provides a magnetic disk having a hole in the center, wherein the disk thickness is...
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WO/2023/192965A1 |
Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. Differential programming can apply a program cycle to multiple memory cells concurrently, detect a program event for one (...
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WO/2023/192966A1 |
Configurable and reconfigurable solid state electronic devices for performing matrix multiplication are provided. The solid state electronic devices at least in part utilize a resistive non-volatile memory circuit for storing data states...
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WO/2023/191711A1 |
Embodiments of the disclosure provide a device-cloud collaboration-based image processing method and apparatus, an electronic device, a storage medium, a computer program product and a computer program. The method comprises: by means of ...
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WO/2023/191935A1 |
Systems, methods, and a computer-readable medium are provided for matching textless elements to texted elements in video content. A video processing system including a textless matching system may divide a video into shots, identify shot...
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WO/2023/187782A1 |
Apparatus including a plurality of non-volatile memory cells of variable resistance organized to perform an instant analog approximation for a reliable neural network inference, by a current distribution governed by conductivity of the c...
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WO/2023/186492A1 |
An apparatus includes a SRAM memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, co...
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WO/2023/184720A1 |
An antifuse address decoding circuit, an operation method, and a memory. The antifuse address decoding circuit comprises: a pre-decoding module (10), configured to decode a programming address of an antifuse storage array and output a pr...
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WO/2023/191919A1 |
Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller det...
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WO/2023/187133A1 |
In the present disclosure, various devices and methods covering a technology for combinatorial liquid handling are disclosed. At least some example embodiments of the devices disclosed herein may include a plurality of liquid dispensers ...
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WO/2023/184707A1 |
Embodiments of the present invention provide a memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate, and a word line, a bit line and a storage unit on one side of the substrate. The stora...
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WO/2023/190541A1 |
Provided is a magnetic recording medium capable of reducing surface dynamic friction of a magnetic layer and achieving good electromagnetic conversion characteristics. This magnetic recording medium is a tape-like magnetic recording me...
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WO/2023/188634A1 |
PROBLEM TO BE SOLVED: To provide a dielectric reproduction device and a dielectric recording and reproduction device that can increase reproduction speed. SOLUTION: A detection means 11 is provided so as to be able to perform a scan rela...
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WO/2023/192795A1 |
An apparatus and system are described to provide an in-memory computing non-volatile flash memory cell array used in a neural network. Each cell includes a Resistive RAM memory (RRAM) and a physical resistor formed from a high resistive ...
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WO/2023/192234A1 |
A hard disk drive enclosure base includes a non-uniform disk shroud surface extending from a top to a floor, the shroud surface including a first portion having a first radius and clearance along the circumference of the shroud surface a...
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WO/2023/192032A1 |
A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.
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WO/2023/188716A1 |
[Problem] Provided are a nonvolatile storage device and a nonvolatile storage system that are capable of suppressing at least one of a current supply amount and variation obtained when simultaneous breakdown of a plurality of memory cell...
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WO/2023/187708A1 |
In general terms the present invention proposes a touchscreen control device 100. The touchscreen control device 100 comprises a manually operable conductive controller 101. The touchscreen control device 100 also comprises first and sec...
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WO/2023/185204A1 |
Embodiments of the present application provide a control method for a ferroelectric memory and a related apparatus, used for stably enabling partial flipping of a ferroelectric device of a ferroelectric memory during write and read opera...
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WO/2023/192083A1 |
The present disclosure relates generally to suspension assemblies for supporting read/write heads adjacent rotating disks in disk drives and more particularly, to a baseplate with an etched hub geometry. Examples of a baseplate of a susp...
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WO/2023/185254A1 |
The present application provides a controller and a control method for a ferroelectric memory array, and a related device. The controller is used for controlling the ferroelectric memory array, which comprises multiple ferroelectric memo...
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WO/2023/190324A1 |
The present invention includes a first and a second memory, and a control circuit that receives write access and read access from the outside, and performs write and read control with respect to the first memory. If a signal prompting a ...
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WO/2023/184813A1 |
A magnetic random access memory (MRAM) as well as a preparation method therefor, and an electronic device. The MRAM comprises: a substrate; bottom electrodes, the bottom electrodes being arranged on one side of the substrate; magnetic tu...
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WO/2023/190086A1 |
A radiation amount sensing device (300) comprises: a power supply circuit (308) that outputs a power supply voltage (Vreg); a temperature sensor unit (320) that functions as a first current source for outputting a first current dependent...
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WO/2023/190210A1 |
A PMIC 200 controls a plurality of power circuits. A nonvolatile memory 260 can be written to repeatedly, and has a plurality of pages. A memory control circuit 214 selects, from the plurality of pages of the nonvolatile memory 260, one ...
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WO/2023/188674A1 |
Provided is a magnetic recording medium capable of increasing reproduction output. The magnetic recording medium is a tape-shaped magnetic recording medium and includes a recording layer. The nucleation magnetic field Hn of the magneti...
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WO/2023/185207A1 |
The present application provides a ferroelectric memory array, a ferroelectric memory and an operation method therefor for reducing the number of SLs to save the layout area and the parasitic capacitance on an LBL. The ferroelectric memo...
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WO/2023/189452A1 |
PROBLEM TO BE SOLVED: To provide a dielectric reproduction device and a dielectric recording and reproduction device that can increase reproduction speed. SOLUTION: A detection means 11 is provided so as to be able to perform a scan rela...
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WO/2023/184658A1 |
Provided in the present application are a data read-write circuit, method and device. The circuit comprises a controller and a memory, wherein the memory is used for decoding an instruction according to a first clock signal sent by the c...
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WO/2023/178788A1 |
A memory test method, a memory test apparatus, a computer readable storage medium, and an electronic device, relating to the technical field of integrated circuits. The memory test method comprises: writing first data into storage units ...
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WO/2023/178868A1 |
A shift register, comprising: an input circuit (1), configured to, in response to signal control provided by a first clock signal end (CK), write into a third node (N3) a signal provided by a signal input end (INPUT); a first control cir...
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WO/2023/183401A1 |
This disclosure provides systems, methods, and apparatus, including: a first magnet with a first remanence value and a first coercivity value, the first magnet having a first cross-sectional area substantially normal to a direction of ma...
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WO/2023/178743A1 |
The present disclosure provides a sense amplifier and a semiconductor memory. Of a body bias adjustment module, a first input end is coupled to a drain of a first N-type transistor, a second input end is coupled to a drain of a second N-...
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WO/2023/178820A1 |
A control method, a semiconductor memory, and an electronic device. The method comprises: decoding a third operation code in a third mode register (303) and a fourth operation code in a first mode register (301) (S101); and in response t...
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WO/2023/178821A1 |
A control method, a semiconductor memory (30), and an electronic device. When the semiconductor memory (30) is in a preset test mode, a first mode register (301) and a second mode register (302) which are related to a data pin (320) are ...
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WO/2023/178824A1 |
A control method, a semiconductor memory, and an electronic device. For a preset test mode, an impedance control policy of a data mask pin is provided to not only define the impedance of the data mask pin in the preset test mode, but als...
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WO/2023/180037A1 |
A system comprises a processor, and a resistive processing unit (RPU) array. The RPU array comprises an array of cells which respectively comprise resistive memory devices that are programable to store weight values. The processor is con...
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WO/2023/178607A1 |
A shift register, a gate driving circuit, and a display device. The shift register comprises: an input circuit (1) configured to control, in response to signal control provided by a first clock signal end (CK), a signal provided by a sig...
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WO/2023/178846A1 |
Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory. The signal sampling circuit comprises: a signal input circuit, used for determining, according to a first clock signal, a first chip sele...
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WO/2023/180676A1 |
An apparatus is provided having a memory device and associated access control circuitry, and an additional memory device and associated additional access control circuitry. Redundant data generation circuitry generates, for a given block...
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WO/2023/181959A1 |
The present invention provides a method for producing a magnetic disk, the method using a fluorine-based solvent that exhibits excellent solubility of a highly polar perfluoropolyether compound, while having a low global warming potentia...
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WO/2023/182992A1 |
This specification describes memory controllers for dynamic random-access memory (DRAM). In one aspect, a memory system includes DRAM that includes DRAM banks. The memory system includes a memory controller for managing the DRAM. The mem...
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WO/2023/181624A1 |
The present invention reduces power consumption of a nonvolatile memory employing a resistance change element. In a memory cell array, a predetermined number of memory cells each including a resistance change element and a switching el...
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