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Patent Searching and Data


Matches 601 - 650 out of 858,320

Document Document Title
WO/2019/031226A1
This spin current magnetoresistive effect element is provided with: a magnetoresistive effect element; a spin orbit torque wire which extends in a first direction intersecting a stacked direction of the magnetoresistive effect element, a...  
WO/2019/032206A1
An optical data-recording system comprises a laser, a dynamic digital hologram, an electronic controller, and a scanning mechanism. The dynamic digital hologram includes a plurality of holographic zones, and is configured to direct the i...  
WO/2019/027727A1
An example apparatus comprises a first portion of an array of memory cells, a second portion of the array of memory cells, a first register corresponding to the first portion, and a second register corresponding to the second portion. Th...  
WO/2019/027741A1
Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includ...  
WO/2019/026720A1
[Problem] To provide a polarization beam splitter that can have reduced size and weight relative to the prior art. [Solution] This polarization beam splitter has a translucent substrate and a hologram layer provided on the front surface ...  
WO/2019/027938A1
Techniques for verifying a magnetic tape are disclosed. The techniques include obtaining a position signal generated by reading a magnetic tape using a stationary tape head. Next, a simulated current for adjusting a position of the tape ...  
WO/2019/024481A1
A shifting register and a driving method therefor, a grid driving circuit, and a display device, which belong to the technical field of displaying. The shifting register comprises: a forward scanning input sub-circuit (1) for pre-chargin...  
WO/2019/027576A1
A hermetically-sealed container for one or more data storage devices may include a first container part or base including a planar main portion, a plurality of sidewalls extending from the main portion, and a plurality of diffusion lengt...  
WO/2019/027719A1
The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a...  
WO/2019/025896A1
Improved spin hall MRAM designs are provided that enable writing of all of the bits along a given word line together using a separate spin hall wire for each MTJ. In one aspect, a magnetic memory cell includes: a spin hall wire exclusive...  
WO/2019/026474A1
A submount (100) comprises a substrate (110), the substrate (110) having: a first surface (101); a second surface (102) that is substantially perpendicular to the first surface (101); a third surface (103) that is substantially perpendic...  
WO/2019/028335A1
An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding ...  
WO/2019/027862A1
Utilizing the topological character of patterns in 3D structures is beneficial for information storage, magnetic memory and logic systems. One embodiment describes the use of topological knots, exemplified by a Möbius strip, in which a ...  
WO/2019/027544A1
In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto refresh mode. A significa...  
WO/2019/026197A1
Disclosed is a semiconductor storage device such as a DRAM or the like wherein, in order to solve a row hammer problem, a row control circuit is provided which latches, as a victim address by a prescribed row address latch method, a targ...  
WO/2019/027937A1
Techniques for performing precise tracking in optical tapes are provided. The techniques include providing and using a servo pattern on an optical tape. The servo pattern includes a first set of parallel physical grooves slanted in a fir...  
WO/2019/027805A1
Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple volta...  
WO/2019/027916A1
Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit,...  
WO/2019/027799A1
Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibrat...  
WO/2018/181901A9
Provided is a cleaning solution composition which: does not damage SiO2, Si3N4, Si, etc., forming a layer on the substrate surface, when cleaning a surface of a semiconductor substrate or a glass substrate; can be used under processing c...  
WO/2019/023000A1
A superconducting bidirectional current driver (10) is disclosed. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch...  
WO/2019/022811A1
Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a dummy memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, ...  
WO/2019/021078A1
The present disclose concerns an apparatus (5) for generating a magnetic field (60) comprising a plurality of permanent magnets (51, 52) arranged in a plane, each magnet (51, 52) being spatially separated along the plane from the adjacen...  
WO/2019/022837A1
Disclosed are techniques for minimizing performance degradation due to refresh operations in a dynamic volatile memory sub-system. In an aspect, a refresh scheduler coupled to the dynamic volatile memory sub-system generates a batch memo...  
WO/2019/019608A1
A shift register circuit, a scan driving circuit, an array substrate and a display apparatus. The shift register circuit has an input end (IN) and an output end (OUT), and comprises: an input module (11), which is respectively connected ...  
WO/2019/023042A1
Methods, systems, and devices for varying a filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines be...  
WO/2019/021368A1
A conductive section (10) electrically connected to a bracket (2) has electric resistivity that is smaller than that of the bracket (2) and that of a navigation chassis (3), and conducts a noise current to a connecting section (7) via a ...  
WO/2019/019550A1
Disclosed in the present invention are a self-adaptive LDPC code error correction code system and method applied to a flash memory. The system and method can improve the error correction capability of the error correction code in the fla...  
WO/2019/021498A1
This semiconductor storage device includes: a first memory string that includes a first memory cell; a bit line; a sense amplifier that includes a latch circuit; a data register that is connected to the sense amplifier and that transmits...  
WO/2019/022732A1
Embedded non-volatile memory structures having bilayer selector elements are described. In an example, a memory device includes a wordline. A bilayer selector element is above the wordline. The bilayer selector element includes a ferroel...  
WO/2019/022952A1
Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to ...  
WO/2019/023049A1
The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of th...  
WO/2019/022815A1
A memory cell includes a VCMA magnetoelectric memory element and a two-terminal selector element connected in series to the magnetoelectric memory element.  
WO/2019/022804A1
Devices (10) and methods (200) include receiving a command at a command interface (14) to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register...  
WO/2019/023700A1
An 8-transistor (8T) static random access memory (SRAM) cell is provided. The SRAM cell includes a first inverter and a second inverter that are cross-coupled to define first and second storage nodes. The SRAM cell also includes a first ...  
WO/2019/021342A1
A programmable display according to the present invention is provided with: a storage unit for storing a master video serving as a reference video from among a plurality of videos to be synchronously played back, a slave video serving as...  
WO/2019/019920A1
A resistive random-access memory (ReRAM) includes a hybrid memory cell. The hybrid memory cell includes: (a) a left resistance-switching device comprising a first terminal and a second terminal, (b) a right resistance-switching device co...  
WO/2019/020553A1
The invention relates to a layer structure comprising a photopolymer layer B and an at least partially hardened protective layer C, a process for manufacturing the layer structure of the invention, a kit of parts, the use of an at least ...  
WO/2019/019527A1
Provided are a solid-state disk storage assembly and a solid-state disk, belonging to the technical field of storage devices. The solid-state disk storage assembly comprises an installation framework (10), a printed circuit board (20) ob...  
WO/2019/022810A1
Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the cr...  
WO/2019/021652A1
This optical recording medium is provided with a first disk, a second disk and an adhesive layer that bonds the first disk and the second disk to each other. Each one of the first disk and the second disk comprises: a substrate which has...  
WO/2019/022921A1
A method and apparatus for cropping annotated images are provided herein. During operation an image will be analyzed to determine any annotation existing within the image. When annotation exists, the annotated portion is cropped and disp...  
WO/2019/023101A1
Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line...  
WO/2019/023253A1
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a me...  
WO/2019/020537A1
The present invention concerns a differential memristive circuit (27). The circuit comprises (a) a normaliser (11); (b) a first memristor (D pos ) connected between a first top node (V topp ) and a first bottom node (Vbotp), the first me...  
WO/2019/017601A1
A multimedia player according to one technical aspect of the present invention may comprise: a multimedia reproducing unit for reproducing a video or music; a gradation information generating unit for quantifying additional information r...  
WO/2019/015613A1
Provided are an electronic-book voice playback method, apparatus, and terminal device; according to a voice playback instruction used for instructing an electronic book to perform voice playback, content of a to-be-played electronic book...  
WO/2019/018634A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented i...  
WO/2019/015630A1
A shift register unit, a driving method, a gate drive circuit, and a display device are provided. The shift register unit comprises: a starting module configured to control, under the control of a first clock signal input, a first node t...  
WO/2019/014985A1
A method for recording and restoring sound and smell, based on crystal forming characteristics. The method comprises the following steps: according to a sound wave signal or smell molecules, controlling a supersaturated solution to be cr...  

Matches 601 - 650 out of 858,320