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Patent Searching and Data


Matches 601 - 650 out of 856,854

Document Document Title
WO/2018/140102A1
Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lin...  
WO/2018/137248A1
A DVD player, comprising an audio interface (102), a button (103), and a remote control receiver (104) respectively connected to a controller (101), and also comprising a voice processor (105) and a flash memory chip (106), the voice pro...  
WO/2018/139249A1
The purposes of the present invention are to effectively achieve protection by way of a cap layer, reduce adverse effects caused by the cap layer, and achieve desired magnetoresistance characteristics, when forming a magnetoresistance ef...  
WO/2018/139235A1
The optical unit pertaining to the present invention is provided with: a sleeve-shaped first optical device holding body having a first holding part for holding a first optical device, and a first fitting margin part extending from the f...  
WO/2018/140434A1
Video information defining video content may be accessed. One or more highlight moments in the video content may be identified. One or more video segments in the video content may be identified based on one or more highlight moments. Der...  
WO/2018/140125A1
A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface ...  
WO/2018/140221A1
In some aspects, a calibration method includes performing a write/read test for each one of multiple combinations of write/read delay settings, wherein each one of the multiple combinations of write/read delay settings includes one of a ...  
WO/2018/139092A1
A resonator 1 is provided with a magnetoresistive effect element 2, an external magnetic field application unit 3, and an energy-imparting unit 4. The magnetoresistive effect element 2 includes: a magnetization fixed layer 21 having magn...  
WO/2018/140579A1
A disk drive is provided with an enclosure and a disk mounted for rotation within the enclosure. The disk drive is also provided with a head mounted for rotation within the enclosure and adapted to engage the disk, a housing defining a c...  
WO/2018/140203A1
An audio processing circuit may have a first path for processing multi-bit audio signals in parallel with a second path for processing single-bit audio signals. The parallel paths may share a common input node for receiving audio data an...  
WO/2018/136601A1
Embodiments of the present disclosure include an apparatus. The apparatus includes a voltage supply line, a sense circuit coupled to the voltage supply line, and a bleeder circuit. The sense circuit is configured to sense a voltage level...  
WO/2018/135336A1
Provided is a playback device in which a playback means plays content-to-be-played in accordance with a playlist. A display control means displays the playlist in a first region of a display unit and displays objects of playable content ...  
WO/2018/136270A1
Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output ci...  
WO/2018/134562A1
Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in(volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static data wit...  
WO/2018/135258A1
The present invention creates a system that allows MMT formatted data to be recorded onto a medium and played back as BDAV or SPAV format data. A stream file constituted by a TLV packet string that stores the MMT formatted data and a pla...  
WO/2018/135268A1
An information processing device comprises: a rail member attached to a drive unit; a drive case housing the drive unit withattached rail member; and a bolt member having a lock. The rail member has an opening. The drive case has an open...  
WO/2018/135655A1
This wiring circuit board is provided with a metal support substrate, an insulating layer and conductor layer disposed on one thickness-directional side of the metal support substrate, a gold plating layer disposed on the other thickness...  
WO/2018/135210A1
The purpose of the present invention is to make it possible to efficiently generate a variety of videos matching diverse needs of users, and enable a user to view a video matching their own request. A video distribution system for genera...  
WO/2018/136124A1
This document describes apparatuses and techniques for integrated DRAM with low-voltage swing I/O. In some aspects, a dynamic random access memory (DRAM) die and application processor (AP) die are mounted to a system-in-package (SiP) die...  
WO/2018/135259A1
The present invention creates a system that allows MMT formatted data to be recorded onto a medium and played back as BDAV or SPAV formatted data. An MMT formatted stream file that stores MMT formatted data as playback data and a playbac...  
WO/2018/136212A1
A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write a...  
WO/2018/135354A1
An objective of the present invention is to sense, by a capacitance sensor, a foreign object which is attached to the inner part of a card reader for illicit purposes, as well as to reduce the probability of misidentifying a card as said...  
WO/2018/136003A1
Various embodiments may relate to a memory cell. The memory cell may include a first cell electrode, a first insulator layer and a first magnetic free layer between the first cell electrode and the first insulator layer. The memory cell ...  
WO/2018/136187A1
Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines...  
WO/2018/130929A1
The present invention efficiently reduces the power consumption of a semiconductor device. The semiconductor device comprises a power supply management device, a cell array, and a peripheral circuit for driving the cell array. The cell a...  
WO/2018/132207A1
A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding...  
WO/2018/130954A1
Provided is a novel semiconductor device. The semiconductor device has a function whereby the pixel selection intervals are changed according to the distance from a drive circuit. Specifically, if the distance between a first pixel and t...  
WO/2018/132074A1
There is provided a memory device including a memory cell configured to store an input data bit written thereto; a memory sensor configured to sense a parameter associated with a state of the memory cell; a detector configured to determi...  
WO/2018/131507A1
Provided is a magnetic recording medium for which the shortest recording wavelength is 75 nm or less and which is used in a recording and reproducing device. The magnetic recording medium includes a recording layer containing a powder of...  
WO/2018/130931A1
To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power sup...  
WO/2018/132834A1
In an example embodiment, an audio device is provided with one or more processors and a computer-readable tangible medium with instructions stored thereon that, when executed, direct the one or more processors to access a target audio fi...  
WO/2018/129928A1
A shift register circuit, comprising an initialization circuit (140), a first node control circuit (110), a second node control circuit (120), and an output circuit (130). The initialization circuit (140) is configured to set a first nod...  
WO/2018/132186A1
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the stri...  
WO/2018/132514A1
An intelligent virtual assistant is provided for respectively customizable interactive audio/video content to each of a plurality of computing devices during a networked communication session. Input is received from at least one device, ...  
WO/2018/132595A1
A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testin...  
WO/2018/126716A1
A shift register unit (100) and a driving method thereof, a gate driving device, and a display device. The shift register unit (100) comprises: an input circuit (11), wherein a first end thereof receives an input signal (INPUT) of the sh...  
WO/2018/128769A1
Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In...  
WO/2018/127089A1
A storage and transfer apparatus (100) for mass transfer of a plurality of data discs (110) to trays (124) of a plurality of stacked disc drives (120) is disclosed. The storage and transfer apparatus (100) may store a plurality of discs ...  
WO/2018/126741A1
A shift register circuit, which comprises a setting circuit (110), a first reset circuit (120), a first control circuit (130), and an output circuit (140). The output circuit (140) is configured to change, in response to a first clock si...  
WO/2018/129407A1
Systems and methods for providing audio-file loop-playback functionality are provided. The system includes a processor that performs a method including setting a playback loop start-point based on a first selection of a button; setting a...  
WO/2018/129324A1
Systems, methods and computer-readable media are provided for capturing audio that is memorable. Buffered audio is stored in a first device over a recent interval such as 5 minutes. In the absence of an indication a circular buffer is us...  
WO/2018/126754A1
A shift register comprises an input module (1), a reset module (2), a node control module (4), a voltage level maintenance module (3), a first output module (5), and a second output module (6). The shift register can ensure normal output...  
WO/2018/129388A1
Systems and methods for generating a visual color display of audio-file data are provided. The system includes a processor that performs a method including receiving audio-file data; generating filtered-audio data by processing the audio...  
WO/2018/129070A1
An electric motor including a coil assembly having a plurality of coils which may be arranged in the shape of a cylinder. The motor further includes a rotor including a plurality of outer magnets configured as a first Halbach cylinder su...  
WO/2018/129418A1
A DJ media player is provided. The DJ media player includes a display to show audio playback information, a patter used to control audio playback, a light emitting element for displaying different colors, and an interface located on the ...  
WO/2018/128768A1
Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first ban...  
WO/2018/126691A1
A shift register unit (100), comprising an input circuit (110), a reset circuit (120), a noise reduction circuit (130) and an output circuit (140). The input circuit (110) is configured to control a voltage of a first node (P) according ...  
WO/2018/128714A1
Systems and method are directed to reducing power consumption of a memory based on enabling partial page access. Based on system conditions such as operating frequency, access size for one or more memory access requests are determined. T...  
WO/2018/128778A1
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O...  
WO/2018/128320A1
An electronic device according to various embodiments of the present invention includes: a microphone; a communication module; a memory; and at least one processor, wherein the processor can receive and record a voice through the microph...  

Matches 601 - 650 out of 856,854