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Patent Searching and Data


Matches 501 - 550 out of 858,320

Document Document Title
WO/2019/041827A1
A shift register unit for a gate driver circuit (GOA), a gate driver circuit comprising the shift register unit, and a driving method applied to the shift register unit. The shift register unit comprises: an input sub-circuit (110), conf...  
WO/2019/046084A1
Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the eras...  
WO/2019/045906A1
An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable ch...  
WO/2019/046032A1
Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable devi...  
WO/2019/046105A1
Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a sign...  
WO/2019/046051A1
Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage componen...  
WO/2019/044061A1
To perform power-supply voltage control suited to the internal state of a memory. This memory controller is provided with a memory interface and a control unit. The memory interface is an interface for connection to the memory. The contr...  
WO/2019/046548A1
Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceed...  
WO/2019/046835A1
A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also incl...  
WO/2019/043989A1
A recording method comprises: acquiring a video stream including an independently decodable picture (S21); recording the acquired video stream onto a recording medium (S22); storing a value representing the data size of the picture in a ...  
WO/2019/046326A1
Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, ...  
WO/2019/046370A1
Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND...  
WO/2019/041840A1
A memory unit and a static random access memory. The memory unit comprises : a latch, the latch providing a first memory bit; and the memory unit further comprises a first MOS tube; the gate electrode of the first MOS tube is connected t...  
WO/2019/046104A1
Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time ...  
WO/2019/045951A1
Techniques for flash memory with row redundancy are described herein. In an example embodiment, a semiconductor device comprises an embedded flash memory. The embedded flash memory comprises a memory bank that includes multiple physical ...  
WO/2019/045796A1
The systems and methods (120) provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface (14) of a memory device (10). A state of a chip select signal (CS) is identified. When...  
WO/2019/041291A1
Provided is an information writing method (200) applicable to an NVDIMM comprising an NVDIMM controller and an NVM. The method (200) comprises: an NVDIMM controller receiving a purge command from a host, the purge command being used to c...  
WO/2019/045973A1
Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses is disclosed. In one aspect, a downstream-facing interface (DFI) device determines a polarity of a next synchronization str...  
WO/2019/045882A1
In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-ext...  
WO/2019/041082A1
Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the...  
WO/2019/046230A1
Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one ...  
WO/2019/046044A1
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a ...  
WO/2019/045922A1
Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of an array of volatile memory cells of the apparatus, deter...  
WO/2019/041586A1
A scanning driving circuit and a liquid crystal display. The scanning driving circuit comprises a plurality of cascaded GOA units. Each GOA unit comprises a pull-up circuit (20), a control circuit (10), a transfer circuit (30), a pull-do...  
WO/2019/046065A1
The present disclosure relates to methods and apparatus for processing media content having video content and associated audio content. A method of processing media content having video content and associated audio content comprises the ...  
WO/2019/043719A1
A system for exchanging multimedia content between a guide to a plurality of travelers comprises: a guide mobile device configured for transmitting said voice and video content from said guide, a plurality of traveler mobile devices conf...  
WO/2019/045786A1
A memory device includes a data path having a data bus. The memory derive further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively co...  
WO/2019/045794A1
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events...  
WO/2019/041584A1
A scanning driving circuit (20, 701) for a light emitting diode display, and a display panel (70). The scanning driving circuit (20, 701) comprises a plurality of scanning driving units (30) in cascade connection; each stage of the scann...  
WO/2019/046013A1
Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to recei...  
WO/2019/046487A1
An apparatus may be designed to enable a user to receive, record, display, edit, arrange, re-arrange, play, loop, extend, export and import audio and video data. The audio and video data to be organized as, for example, but not limited t...  
WO/2019/045074A1
In the present invention, the surface roughness Rz of the outer peripheral edge of a spacer is set to 1.5 ┬Ám or greater. Thereby, when assembling a hard disc drive device, errors that may occur while pulling out a spacer using a grippin...  
WO/2019/045087A1
A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising: exposing a pattern on a wafer for creating structures for a plurality of memory cells fo...  
WO/2019/045785A1
Memory devices (10) may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device (10) may receive and process signals employing di...  
WO/2019/045981A1
Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells...  
WO/2019/042314A1
A shift register (100), a gate drive circuit (10), a display panel (1), and a driving method. The shift register (100) comprises: an input circuit (110), which is connected to a pull-up node (PU) and an input signal terminal (INPUT) resp...  
WO/2019/045784A1
One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory...  
WO/2019/045931A1
Devices and techniques for random access memory power savings are disclosed herein. Data contained in RAM is compressed in response to obtaining a trigger. Here, the RAM organized into several discrete hardware components with a correspo...  
WO/2019/044370A1
The present invention provides a card reader which, via a simple structure, is capable of detecting a skimming magnetic head attached to the front of a card insertion member provided with a card slot and a skimming magnetic head attached...  
WO/2019/045943A1
A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a r...  
WO/2019/045795A1
A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of...  
WO/2019/046189A1
A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude...  
WO/2019/045913A1
Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw...  
WO/2019/046029A1
In an exmaple, an apparatus includes a memory array separate from a semiconductor, a trigger device separate from the semiconductor and coupled to an access line in the memory array, a select device separate from the semiconductor and co...  
WO/2019/045806A1
A memory device and associated techniques for reducing charge loss in a select gate transistor. A dummy memory cell is weakly programmed using a hot electron injection type of disturb to reduce the movement of holes toward the adjacent s...  
WO/2019/041662A1
A DRAM test device, comprising: a test frame (101) for inserting a DRAM to be tested, a program storage module (102) for storing a test program, a current test module (103) and a test control module (104). The test control module (104) r...  
WO/2019/040501A1
Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, ...  
WO/2019/040891A1
Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration are disclosed. In one aspect, an MRAM bit cell includes a magnetic tunnel junction (MTJ) ...  
WO/2019/040304A1
Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that repres...  
WO/2019/038848A1
The present invention addresses the problem that, in a system in which graphics are combined with a content video and then transmitted to a display device, the brightness of the graphics fluctuates due to dynamic metadata control. A vide...  

Matches 501 - 550 out of 858,320