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Patent Searching and Data


Matches 501 - 550 out of 857,845

Document Document Title
WO/2019/022732A1
Embedded non-volatile memory structures having bilayer selector elements are described. In an example, a memory device includes a wordline. A bilayer selector element is above the wordline. The bilayer selector element includes a ferroel...  
WO/2019/022952A1
Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to ...  
WO/2019/023049A1
The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of th...  
WO/2019/022815A1
A memory cell includes a VCMA magnetoelectric memory element and a two-terminal selector element connected in series to the magnetoelectric memory element.  
WO/2019/022804A1
Devices (10) and methods (200) include receiving a command at a command interface (14) to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register...  
WO/2019/023700A1
An 8-transistor (8T) static random access memory (SRAM) cell is provided. The SRAM cell includes a first inverter and a second inverter that are cross-coupled to define first and second storage nodes. The SRAM cell also includes a first ...  
WO/2019/021342A1
A programmable display according to the present invention is provided with: a storage unit for storing a master video serving as a reference video from among a plurality of videos to be synchronously played back, a slave video serving as...  
WO/2019/019920A1
A resistive random-access memory (ReRAM) includes a hybrid memory cell. The hybrid memory cell includes: (a) a left resistance-switching device comprising a first terminal and a second terminal, (b) a right resistance-switching device co...  
WO/2019/020553A1
The invention relates to a layer structure comprising a photopolymer layer B and an at least partially hardened protective layer C, a process for manufacturing the layer structure of the invention, a kit of parts, the use of an at least ...  
WO/2019/019527A1
Provided are a solid-state disk storage assembly and a solid-state disk, belonging to the technical field of storage devices. The solid-state disk storage assembly comprises an installation framework (10), a printed circuit board (20) ob...  
WO/2019/022810A1
Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the cr...  
WO/2019/021652A1
This optical recording medium is provided with a first disk, a second disk and an adhesive layer that bonds the first disk and the second disk to each other. Each one of the first disk and the second disk comprises: a substrate which has...  
WO/2019/022921A1
A method and apparatus for cropping annotated images are provided herein. During operation an image will be analyzed to determine any annotation existing within the image. When annotation exists, the annotated portion is cropped and disp...  
WO/2019/023101A1
Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line...  
WO/2019/023253A1
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a me...  
WO/2019/020537A1
The present invention concerns a differential memristive circuit (27). The circuit comprises (a) a normaliser (11); (b) a first memristor (D pos ) connected between a first top node (V topp ) and a first bottom node (Vbotp), the first me...  
WO/2019/017601A1
A multimedia player according to one technical aspect of the present invention may comprise: a multimedia reproducing unit for reproducing a video or music; a gradation information generating unit for quantifying additional information r...  
WO/2019/015613A1
Provided are an electronic-book voice playback method, apparatus, and terminal device; according to a voice playback instruction used for instructing an electronic book to perform voice playback, content of a to-be-played electronic book...  
WO/2019/018634A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented i...  
WO/2019/015630A1
A shift register unit, a driving method, a gate drive circuit, and a display device are provided. The shift register unit comprises: a starting module configured to control, under the control of a first clock signal input, a first node t...  
WO/2019/018462A3
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further includ...  
WO/2019/014985A1
A method for recording and restoring sound and smell, based on crystal forming characteristics. The method comprises the following steps: according to a sound wave signal or smell molecules, controlling a supersaturated solution to be cr...  
WO/2019/017264A1
The purpose of the present invention is to provide a shift register that is capable of suppressing occurrence of an erroneous operation caused by off-leakage at a thin-film transistor and stopping a shifting operation to be performed at ...  
WO/2019/018462A2
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further includ...  
WO/2019/015336A1
A shift register unit (100), a scan drive circuit (10), an array substrate (1), a display device and a drive method. The shift register unit (100) comprises an input circuit (11), a reset circuit (12), an output circuit (13) and a pull-d...  
WO/2019/016539A1
A switching resistor comprises a dielectric layer disposed between a first electrode layer and a second electrode layer, the switching resistor having a high resistance state and a low resistance state. The switching resistor is responsi...  
WO/2019/015355A1
A scanning shift circuit and a driving method therefor, a touch control shift circuit and a driving method therefor, a gate drive circuit, a touch control drive circuit and a display device. The scanning shift circuit comprises: an input...  
WO/2019/015309A1
A shift register unit (100), a method for driving the shift register unit (100), a gate drive circuit, an array substrate and a display device. The shift register unit (100) comprises: an input sub-circuit (101), a first end of the input...  
WO/2019/018530A1
Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver sec...  
WO/2019/010956A1
A shift register unit and a driving method therefor, a gate driving circuit, and a display apparatus. The shift register unit comprises: an input circuit (10), an output circuit (20), a pull-down control circuit (30) and a pull-down circ...  
WO/2019/012207A1
The invention concerns an RFID radio tag (1) for a vinyl disc comprising at least one electronic chip (2) and an antenna (5), configured as a spiral and wherein the central part (9) of the radio tag is provided with a through-hole. The r...  
WO/2019/013925A1
A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a f...  
WO/2019/012737A1
[Problem] To provide various means for efficiently attenuating vibrations applied to a turntable to dramatically reduce the noise picked up by a needle, thereby allowing a listener to hear original sounds buried in noise that prevents th...  
WO/2019/013775A1
A computing device that includes a plurality of memory devices and firmware to provide a migration data storage option that reserves a portion of a memory device to store, at least, encrypted metadata describing the physical layout infor...  
WO/2019/011996A1
A method for saving digital data on a photographic medium (1) in particular a strip, preferably a strip of 35 mm film, comprising the step involving imaging, on the medium (1), blocks (14) of pixels encoding the information to be saved a...  
WO/2019/010952A1
A shift-register circuit, a driving method thereof, a gate-driving circuit and a display apparatus are disclosed. The shift-register circuit includes an input sub-circuit (10), a reset sub-circuit (20), an output sub-circuit (30), a pull...  
WO/2019/011749A1
An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeate...  
WO/2019/014131A1
A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over...  
WO/2019/013955A1
Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuit...  
WO/2019/013953A1
Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string c...  
WO/2019/013851A1
A semiconductor device includes a clock divider (72) that receives a clock signal (58) and generates even and odd clock signals (74, 76). The clock signal (58) includes a first frequency, while the even and odd clock signals (74, 76) eac...  
WO/2019/010044A1
One embodiment facilitates mitigating write amplification in a phase change memory-based storage device. During operation, the system receives, by a controller of the storage device, data to be stored in a phase change memory (PCM) of th...  
WO/2019/007043A1
A gate drive unit circuit and a driving method therefor, a gate drive circuit and a display apparatus. The gate drive unit circuit comprises: a shift register (SR) and several drive signal output sub-circuits (5), wherein each of the dri...  
WO/2019/010251A1
Methods and systems are provided for enhanced audio experiences in VR/AR applications. The apparatuses of this disclosure are adapted to record multiple binaural stereo pairs and play back select binaural pairs corresponding to user's he...  
WO/2019/007049A1
A shift register (SRi), a gate driving circuit (140) and a driving method therefor, and a liquid crystal display (10). The shift register (SRi) comprises: a pull-up sub-circuit (201), configured to set the potential of a pull-up node (PU...  
WO/2019/008186A1
A method is shown for providing a user interface for a 3D environment of 360° images. The method includes displaying a first 360 degree image in a sequence of 360 degree images; receiving user input to interact with one of a plurality o...  
WO/2019/008483A1
Provided is a semiconductor device having a large memory capacity per unit surface area. The invention relates to a memory cell having a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitive e...  
WO/2019/009086A1
This semiconductor laser device (1) is provided with: a lower electrode block (10) which has a first terminal hole and has a first and second connection hole on both sides of a recess that houses a submount where a semiconductor laser el...  
WO/2019/009082A1
The present technique relates to a signal processing device, a signal processing method, and a program that allow one DSD signal to also support a PCM signal output. A distribution device comprises: an extraction unit for extracting, whe...  
WO/2019/009876A1
A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite f...  

Matches 501 - 550 out of 857,845