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Patent Searching and Data


Matches 501 - 550 out of 855,240

Document Document Title
WO/2018/032960A1
An array substrate and a display panel, the array substrate comprising shift registers (Gn) corresponding to each gate line. A transistor, in shift registers of various stages, connected with a corresponding-stage gate line (gate n) and ...  
WO/2018/028195A1
A shift register for a display device. The shift register may include a shift register processing circuit (10) and a control circuit (20). A first terminal of the control circuit(20) may be coupled to an output terminal (Qn) of the shift...  
WO/2018/028071A1
An audio playback system and a hearing protection method for playing back an audio using the same system, comprising: an audio server end (1) and a terminal device (2), the audio server end (1) and the terminal device (2) being connected...  
WO/2018/031187A1
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vi...  
WO/2018/029584A1
A mass storage devices package (10) includes a structure comprising a stack of two or more mass storage devices (14) of same dimensions, each having a form factor having two opposite main surfaces. The mass storage devices (14) are super...  
WO/2018/031474A1
Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell...  
WO/2018/031827A1
A design for a cooperative live action virtual reality experience is described. A client makes use of a 360-degree display unit to play a 360-degree video file, a corresponding audio file, and an annotati on requesting the user to make a...  
WO/2018/031217A1
Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities...  
WO/2018/027730A1
A method and system for synchronisation in piano video teaching, the method comprising the following steps: obtaining an utterance of a user (S101); searching within a playback piano video for a video progress point which is the same as ...  
WO/2018/026476A3
Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and ea...  
WO/2018/024953A1
An audio decoding and reading system comprises a computing module (1), a high-fidelity module (2) and a buffer-memory assembly (3b) which is intermediate between the computing module and the high-fidelity module. The buffer memory assemb...  
WO/2018/026475A2
Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage ce...  
WO/2018/025769A1
Provided is an aluminum alloy sheet for magnetic disc substrates, etc. for which plating surface smoothness after plating layer formation is excellent and which can be produced at low cost. This aluminum alloy sheet for magnetic disc sub...  
WO/2018/026475A3
Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage ce...  
WO/2018/025364A1
This record player (1) includes: an analog record player main body (2); a dust case (3) openably and closably attached to the analog record player main body (2); and a stopper (5) provided inside the dust case (3) and locking a record ja...  
WO/2018/026629A1
A management controller may be configured to control connectivity among a host system processor, a primary ROM, and a recovery ROM in accordance with a plurality of modes of operation including at least a normal mode that occurs in respo...  
WO/2018/026946A1
A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semi...  
WO/2018/026458A1
A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to selec...  
WO/2018/026476A2
Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and ea...  
WO/2018/026529A1
Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of t...  
WO/2018/026815A1
A random access memory (RAM) includes a bit-line, a source-line, a memory cell connected to the bit-line and the source-line, and a read/write circuit connected to the bit-line and the source-line and including a negative differential re...  
WO/2018/022385A1
A memory cell including a magnetic Josephson junction (MJJ) device is provided. The MJJ device (300) includes a free magnetic layer (310), a non-magnetic layer (320), and a fixed magnetic layer (312). The free magnetic layer comprises a ...  
WO/2018/022172A1
A system and method is disclosed for an electronic device, such as a non-volatile memory associated with a host, to determine a current sourcing capability of the host and to adjust performance characteristics of the electronic device ba...  
WO/2018/022515A1
An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device m...  
WO/2018/022188A1
A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to initiate a read operation to retrieve data from the non-volatile memory. The controller is also con...  
WO/2018/022662A1
A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of an endurance event, a retention timer event or a read disturb event at a closed b...  
WO/2018/022835A1
The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The control...  
WO/2018/016294A1
The objective of the present invention is to enable MMT format data to be recorded onto media as BDAV format data, and to enable a display process for a recorded content list, as well as reproduction by means of a BDAV-compliant applicat...  
WO/2018/017438A1
A cinemagraph is generated that includes one or more video loops. A cinemagraph generator receives an input video, and semantically segments the frames to identify regions that correspond to semantic objects and the semantic object depic...  
WO/2018/017448A1
A method for synchronizing audio playback by the audio playback devices of a group with at least two audio playback devices, where the group is part of a larger zone of audio playback devices, and where one audio playback device of the z...  
WO/2018/016176A1
A neural network circuit according to an embodiment of the present invention includes a storage unit (2) comprising memristors (G11 through G33) serving as storage elements connected to each other in a grid pattern. When a control unit (...  
WO/2018/015839A3
A CAM memory (Content Addressable Memory) is described, comprising a plurality of memory cells (2), organized in rows and columns, adapted to store a plurality of data words, a plurality of bit lines (BL, BLN) for receiving the bits of a...  
WO/2018/016435A1
[Problem] It is not conventionally possible to suitably indicate a location where a transition from one scene to another scene occurs. [Solution] A video processing device provided with: a change information acquisition unit which acquir...  
WO/2018/017189A1
Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming op...  
WO/2018/017990A1
A computer-implemented method is described for configuring interaction zones for a virtual reality environment. The method may include defining a plurality of scenes, each scene including a plurality of selectable scene cuts and defining...  
WO/2018/015118A1
The present invention relates to a system for obtaining medicament related information of specific medicaments, the system comprising a device (10, 50) for obtaining medicament related information, the device comprising a recording unit,...  
WO/2018/014622A1
Disclosed are a method, device and system for playing music, wherein the method comprises: receiving manipulation state information sent by a manipulation terminal, the manipulation state information being determined according to the num...  
WO/2018/014250A1
An adsorbent breather assembly for filtering contaminants such as particulars and vapor phase contaminants, e.g. volatile organic compounds, for use with electronic devices can include a blocking region adjacent to the adsorbent filter l...  
WO/2018/017188A1
Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate ...  
WO/2018/017677A1
A three dimensional (3-D) integrated circuit (IC) including a substrate having a substrate surface. A first semiconductor device having a first electrical contact and is formed in a first area of the surface on a first plane substantiall...  
WO/2018/015839A2
A CAM memory (Content Addressable Memory) is described, comprising a plurality of memory cells (2), organized in rows and columns, adapted to store a plurality of data words, a plurality of bit lines (BL, BLN) for receiving the bits of a...  
WO/2018/016178A1
The purpose of the present invention is to provide a shift register circuit and a display panel that appropriately control the back-gate voltage of a transistor using a simple configuration at low cost. Each of a plurality of shift regis...  
WO/2018/017812A3
A lid including one or more messages relating to a product is provided. The lid can store and play one or more audio messages on an audio device attached thereto. The audio messages can be recorded onto the audio device, loaded onto the ...  
WO/2018/017440A1
Described are various technologies that pertain to automatically generating looped videos or cinemagraphs by selecting objects to animate from an input video. In one implementation a group of semantically labeled objects from an input vi...  
WO/2018/011926A1
Provided is a storage device comprising a memory cell array that stores data; a control circuit that controls the memory cell array according to commands; and a receiver which enters an active state on the basis of operations results of ...  
WO/2018/013133A3
Examples of a printhead assembly comprising an Erasable Programmable Read-only Memory (EPROM) having a predefined number of banks, with EPROM cells arranged in rows and columns in each of the banks are described. In one example, the prin...  
WO/2018/011686A1
The present disclosure provides a system and method for enabling navigation to one or more discrete segments of a real time dynamic and adaptive non-linear, non-sequentially assembled video. The method includes reception of a set of pref...  
WO/2018/012740A1
A storage cell of a ternary content addressable memory comprises a first storage unit, a second storage unit, and a comparison unit. The first storage unit stores first data. The second storage unit stores second data. The comparison uni...  
WO/2018/009182A1
A resistive RAM memory cell and array are described that include an electroforming functionally. One example includes a first resistive memory material, a first electrode on one side of the first resistive memory material, a second resis...  
WO/2018/007925A1
A method of generating an audio visual identification comprising the steps of extracting an audio sequence from a randomly generated noise generator, such as a white or pink noise generator, and saving the sequence as an audio tone; atta...  

Matches 501 - 550 out of 855,240