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Matches 551 - 600 out of 845,016

Document Document Title
WO/2016/144362A1
Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may...  
WO/2016/144508A1
An electronic device is configured to: while presenting media content at a first non-zero playback speed, detect a press input by a first contact on a first media control; and, in response to detecting the press input: determine whether ...  
WO/2016/144726A1
The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of ...  
WO/2016/145166A1
A tape head is provided for use with a tape drive that is configured to receive a length of tape. The tape head includes a head body including at least one head element for performing read and/or write operations on the tape, and a prote...  
WO/2016/144436A3
A device includes a first magnetic tunnel junction (MTJ) element having a first read margin and a second MTJ element having a second read margin. The first read margin is greater than twice the second read margin. The device also include...  
WO/2016/143168A1
A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated...  
WO/2016/144434A1
A push-pull resistive random access memory cell circuit includes an output node, a word line, and first and second bit lines. A first resistive random access memory device is connected between the first bit line and the output node and a...  
WO/2016/145012A1
An apparatus relates generally to a reduced load memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips (123) coupled to the circuit platform. Each memory chip has a plurality of memory dies (40...  
WO/2016/145328A2
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile ...  
WO/2016/143858A1
The present invention addresses the problem of providing an Ni-based sputtering target material in which permeability is low, a strong magnetic flux leakage is obtained, and the usage efficiency in magnetron sputtering is high. In order ...  
WO/2016/143726A1
In relation to recording and playback of a hologram, consideration has not thus far been given to crosstalk among adjacent pages with respect to the recording in a stack, which is a unit of multiplexing recording in a given location, whe...  
WO/2016/144335A1
Example implementations relate to releasing an optical disk drive (ODD) from an ODD bracket. For example, a system for releasing an ODD from an ODD bracket includes the ODD, the ODD bracket, and a retention latch for securing the ODD to ...  
WO/2016/145048A1
Systems and methods herein are directed to three-dimensional image sources for an enhanced Pepper's Ghost Illusion. In one embodiment, a contoured bounce is described, allowing for contorting a bounce to different shapes, giving it enhan...  
WO/2016/143383A1
To improve performance of a memory cell that stores therein values corresponding to the current directions. This memory cell is provided with an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplie...  
WO/2016/144398A1
System and method are disclosed for managing storage space of a magnetic storage device. The system may read data from a sector of the storage space and determine whether the data are successfully read from the sector. If it is determine...  
WO/2016/143169A1
According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a firs...  
WO/2016/141666A1
A shift register and a driving method therefor, a gate drive circuit and a display apparatus. The shift register comprises: a first input module (11) for pulling up the potential of a first node under the effect of a signal received by a...  
WO/2016/144813A1
One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second bi...  
WO/2016/139863A1
The purpose of the present invention is to improve data detection capabilities by whitening cross-talk noise from an equalized signal and carrying out binary data detection. In the present invention, multi-input adaptive equalization pro...  
WO/2016/139392A1
Apparatus comprising: an audio analyser configured to determine a spectral flatness value associated with a captured audio signal associated with an audio scene and compare the spectral flatness value against a threshold value;a detectab...  
WO/2016/138734A1
A shift register and drive method thereof, and gate drive circuit, addressing an existing problem in which a gate drive circuit cannot alter an overlap ratio between gate conduction timing. The shift register comprises: an input unit con...  
WO/2016/140889A1
One embodiment describes a quantum memory system. The system includes a plurality of quantum memory cells arranged in an array of rows and columns. Each of the plurality of quantum memory cells can be configured to store a binary logic s...  
WO/2016/139319A1
The invention relates to a method for browsing a collection of P video frames through a user interface comprising N cells disposed along a time line with N
WO/2016/139765A1
The purpose of the present invention is to provide an optical information recording device and an optical information recording method that ensure performance and speed up calculation processing time, and that generate 2D data. In the pr...  
WO/2016/138814A1
A method and device for testing a synchronous dynamic random access memory (SDRAM). The method comprises: acquiring a test policy for testing a specified storage space of an SDRAM, the SDRAM being connected to a field programmable gate a...  
WO/2016/139878A1
[Problem] To provide a storage element having both high information holding characteristics and low power consumption. [Solution] The storage element comprises a fixed layer, a storage layer, an intermediate layer, and a heating layer. T...  
WO/2016/141060A1
A memory device comprises a semiconductor substrate with memory (16) and logic device areas (18). A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region thereb...  
WO/2016/137739A2
The present application is directed to new methods for automatically determining several characteristics of frames in a video sequence and automatically recommending or preparing image output products based on those frame characteristics...  
WO/2016/137670A1
An apparatus includes a static random-access memory (SRAM) and circuitry configured to initiate a correct action. The corrective action may be initiated based on a number of SRAM cells that have a particular state responsive to a power-u...  
WO/2016/137683A3
Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or pro...  
WO/2016/137449A1
In one example in accordance with the present disclosure a method of determining a resistance state of a memristor in a crossbar array is disclosed. In the method, a combined reference-sneak current is determined based on a reference vol...  
WO/2016/137503A1
An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power...  
WO/2016/136518A1
A multilayer film which is obtained by providing at least one surface of a polyester film with a resin layer, and which is characterized in that: the reflectance of the surface of the resin layer at a wavelength of 550 nm is 6.0% or more...  
WO/2016/136528A1
The present invention realizes a shift register circuit that enables a display device to achieve higher definition with as small a number of elements as possible without causing a malfunction. A unit circuit is provided with: a thin film...  
WO/2016/137685A2
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in...  
WO/2016/137734A2
A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a dra...  
WO/2016/137681A3
P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells ("bit cells") are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sen...  
WO/2016/137739A3
The present application is directed to new methods for automatically determining several characteristics of frames in a video sequence and automatically recommending or preparing image output products based on those frame characteristics...  
WO/2016/137889A1
The present disclosure provides a method, apparatus, and computer-readable medium for managing data. A method includes creating, by a first user equipment (UE), a data, and transferring, by the first UE, the data to a server. The method ...  
WO/2016/137760A1
Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank ...  
WO/2016/136748A1
The objective of the present invention is to provide a management system with which it is possible to reduce the required capacity of a storage device, even if the number of events that occur increases, and in which said required capacit...  
WO/2016/137446A1
In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias volt...  
WO/2016/137402A1
A method for data stripping, allocation and reconstruction in an active drive storage system including a plurality of active object storage devices, each of the plurality of active object storage devices including one or more storage dev...  
WO/2016/137717A1
A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells correspond...  
WO/2016/137681A2
P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells ("bit cells") are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sen...  
WO/2016/138457A1
Compounds useful as fluorescent or colored dyes are disclosed. The compounds have the following structure (I), including salts thereof, wherein R1a, R1b, R1c, R1d, R1e, R1f, R2a, R2b, R2c, R2d, R2e, R2f, R2g, R2h, R2i, R2j, x and y are a...  
WO/2016/137678A1
Write-assist circuits for memory bit cells ("bit cells") employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scale...  
WO/2016/136118A1
The present invention provides a magnetic recording medium capable of achieving high density recording by decreasing the bit transition width during the process of heat-assisted recording on a heat-assisted magnetic recording medium. The...  
WO/2016/137685A3
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in...  
WO/2016/137683A2
Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or pro...  

Matches 551 - 600 out of 845,016