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Matches 551 - 600 out of 851,116

Document Document Title
WO/2016/204961A1
Phase compensation in an I/O (input/output) circuit includes a triangular control contour with a simplified generation circuit. A linear control circuit can generate a digital N-bit linear count, and route the least significant M bits [(...  
WO/2016/204922A1
A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of cro...  
WO/2016/202176A1
The present invention relates to the technical field of multimedia synthesis, and provides a method, device and apparatus for synthesizing a media file. The method comprises: receiving a media file template selection instruction inputted...  
WO/2016/204823A1
A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit d...  
WO/2016/203693A1
The purpose of the present invention is to provide a magnetic recording medium in which the surface roughness of a magnetic recording layer can be reduced without adversely affecting the magnetic characteristics of the magnetic recording...  
WO/2016/204940A1
A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second M...  
WO/2016/203631A1
A flash memory controller of the present invention holds a read pattern indicating an execution sequence of read options that specify parameter values for a read from a flash memory chip. The flash memory controller executes error correc...  
WO/2016/204962A1
Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for bet...  
WO/2016/204889A1
Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells couple...  
WO/2016/203341A1
To provide a transistor resistant to short channel effects. This semiconductor device includes: a first electrical conductor provided in the shape of a ring; an oxide semiconductor having an elongated region which passes through to the i...  
WO/2016/204529A1
A memory storage device and method for preventing data loss after a power loss are disclosed. The memory storage method may comprise the steps of: determining, on the basis of the restoration time of a mapping table required by a user, a...  
WO/2016/204826A1
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input vol...  
WO/2016/203397A1
A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a d...  
WO/2016/202517A1
The invention relates to a laser scanner (10), which can comprise at least one galvanometer motor (20, 120) having a motor shaft (30, 130) to which an optical element (40, 140) is fixed, a heat sink (50) and at least one heat pipe (60, 1...  
WO/2016/204851A1
Described are embodiments directed to memory devices, including non-volatile memory (NVM), such as flash memory devices, and/or resistive switching memories (e.g., conductive bridging random-access memory [CBRAM], resistive RAM [ReRAM], ...  
WO/2016/200446A1
A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a ...  
WO/2016/197745A3
A method and device for implementing audio recording. The method comprises: determining the positional relationship between an audio recording object and a microphone array (100); according to the determined positional relationship betwe...  
WO/2016/199233A1
A hologram recording and playback device in which there is a restriction on the number of times a replacement process can be performed in order to record data in high densities, wherein in view of the fact that a failure to perform rewri...  
WO/2016/197384A1
An electronic disc jockeying machine comprising a front housing (1), a bottom housing (2), and a turntable (3). The electronic disc jockeying machine also comprises a turntable functional element (4). The turntable (3) is engagedly conne...  
WO/2016/200721A1
Methods and apparatus for contextual video content adaptation are disclosed. Video content is adapted based on any number of criteria such as a target device type, viewing conditions, network conditions or various use cases, for example....  
WO/2016/201432A1
In one example, a device for creating an event-driven audio file may comprise a processor and an audio engine to, when executed by the processor, receive a configuration file designating a number of device-external data feeds and create ...  
WO/2016/197724A1
A control apparatus and method for realizing a high-voltage read/write power supply. The apparatus comprises: a write branch, which is configured to switch an output voltage into a high voltage that meets a first pre-set condition and is...  
WO/2016/198886A1
The disclosure relates to information storage using magnetic domains or magnetic domain walls, and relates to methods of moving, creating, detecting and transforming the structure of magnetic domain walls using mechanical strain induced ...  
WO/2016/199231A1
Provided are an optical information reproduction device that uses holography and a method therefor allowing the effect of reference light reflected from a disc surface to be reduced, and allowing the data to be stably reproduced. The opt...  
WO/2016/198965A1
According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulat...  
WO/2016/200718A1
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods - which we call Quick Error Detection - Hardware (QED-H) - advantageously quickly dete...  
WO/2016/198830A1
A switching circuit has a threshold device in series with a phase-change material part and comprise a circuit operable as a relaxation oscillator. There is an input for receiving a voltage which is applied to the switching circuit. Appli...  
WO/2016/197745A2
A method for implementing audio recording, a terminal and a computer readable storage medium. The method comprises: determining the positional relationship between an audio recording object and a microphone array; according to the determ...  
WO/2016/200966A1
An electronic temperature switch (10), comprises a measurement circuit (11) that measures temperature and generates an temperature signal corresponding to the sensed temperature; an evaluator circuit (12) that receives said temperature s...  
WO/2016/199346A1
[Problem] To provide an information processing method, program, information processing device, and information processing system which are capable of achieving a high-quality content listening/viewing experience. [Solution] An informatio...  
WO/2016/200675A1
Dynamically managing control information in a storage device, including: querying, by an array management module executing on a storage array controller, the storage device for a location of control information for the storage device, th...  
WO/2016/200837A1
Fabrication, integration and operation of an array of micro-scale singulated electronic and opto- electronic semiconductor devices in flexible, thin and highly reliable format. The array includes power and data management devices that ar...  
WO/2016/197708A1
A recording method and a terminal, the method comprising: within a process of recording audio data, obtaining ith tag information, the ith tag information comprising: an ith tag time point and an ith tag identifier, wherein N ≥ i ≥ 1...  
WO/2016/199229A1
A hologram record-playback device, wherein the diffusion effect of a phase diffusion element is improved while ensuring signal quality, so that high-recording-density recording can be performed. A first phase diffusion filter, which is d...  
WO/2016/198846A1
A system for editing at least one media clip comprising highlighting means to highlight a selected portion of the media clip, recording means to record data in respect of said highlighted portion, and storage means to store said recorded...  
WO/2016/197531A1
A shift register unit and a drive method therefor, and a gate drive circuit and a display apparatus. In the shift register unit, an input module (1) is configured to output a pull-up control signal to a pull-up module (4) according to a ...  
WO/2016/194383A1
The purpose of the present invention is to provide a magnetic recording medium having improved characteristics, and having a laminated structure which includes a seed layer containing (Mg1-xTix)O and a magnetic recording layer containing...  
WO/2016/195637A1
An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurali...  
WO/2016/195873A1
The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a me...  
WO/2016/192046A1
A circuit (100). A first end (108) of a resistive random access memory (102) comprised by the circuit (100) is a first end of the circuit (100). A second end (116) of the resistive random access memory (102) is connected to a first end (...  
WO/2016/195736A1
A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circui...  
WO/2016/191830A1
A memory structure for use in a memory device comprising at least one first layer and at least one second layer: the at least one first layer comprises a plurality of a first element, and the at least one second layer comprises a plurali...  
WO/2016/193908A1
A magnetic device (100) configured to perform an analog adder circuit function and comprising a plurality of magnetic units, each including n magnetic tunnel junction (2, 2', 2", 2"',...) electrically connected in series via a current li...  
WO/2016/195755A1
A thermally and structurally optimized disaster resistant housing for a vertically stacked array of computer digital data storage devices such as hard drives is provided. An external, fire resistant housing has an internally mounted wate...  
WO/2016/194362A1
An image display apparatus according to the present invention includes: a display unit configured to display a moving image based on input moving image data; a determining unit configured to determine whether or not a specific reproducti...  
WO/2016/195940A4
Systems, methods, and computer-readable medium are provided for presenting a synchronized content scrubber. For example, a user device may store digital content items for presentation on a screen of the user device. A user interface may ...  
WO/2016/196835A1
In described examples, an integrated circuit includes a ferroelectric random access memory (FRAM) for storing firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM m...  
WO/2016/194132A1
A semiconductor storage device (1) is equipped with a thin film capacitor (30) that is provided at a position facing a circuit surface (11) of a memory chip (10), said position excluding a center pad region (14). The thin film capacitor ...  
WO/2016/196988A1
A method may include presenting an image capture user interface on a display device of a multipurpose device including a live view portion configured to display a live view of image data currently sensed by an image capture device of the...  
WO/2016/196963A1
Aspects of the present disclosure generally relate to static random access memory (SRAM), and more specifically, to a low-power, row-oriented memory write assist circuit. The SRAM may generally comprise an array of bit cells arranged in ...  

Matches 551 - 600 out of 851,116