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Patent Searching and Data


Matches 551 - 600 out of 855,772

Document Document Title
WO/2018/056105A1
The present technique relates to an information processing apparatus, an information processing method, a program and an information processing system with which a schedule for recording programs listed in a search result can be easily s...  
WO/2018/057766A1
A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condit...  
WO/2018/055455A8
The technology relates to processing one or more audio streams. The processing may include segmenting the one or more audio streams into structural components comprising a tonal stream and a transient stream. The tonal stream and the tra...  
WO/2018/057226A1
An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. T...  
WO/2018/057429A1
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory...  
WO/2018/057228A1
Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with thr...  
WO/2018/057460A1
Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify...  
WO/2018/057137A1
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input...  
WO/2018/055614A1
A method for detecting errors is performed on a data string which includes an information portion and a redundancy portion. The information portion includes two or more sub-strings. The method includes generating respective redundancy wo...  
WO/2018/057191A1
The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to for...  
WO/2018/057400A1
Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connectio...  
WO/2018/057014A1
Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector...  
WO/2018/055455A1
The technology relates to processing one or more audio streams. The processing may include segmenting the one or more audio streams into structural components comprising a tonal stream and a transient stream. The tonal stream and the tra...  
WO/2018/054222A1
A multiple disk loader apparatus includes a plurality of rods. Each rod has a pair of pins extending radially from a side of the rod. The pair of pins are spaced circumferentially around the rod with respect to each other. Each pin has a...  
WO/2018/055768A1
The number of selectable chips is increased without adding signal lines to a general-purpose memory controller. A semiconductor storage device is provided with: a memory controller; a plurality of memory chips; a selection unit connected...  
WO/2018/055733A1
This storage device comprises a first memory cell and a second memory cell adjacent to the first memory cell, and a sequencer which, when reading data from the first memory cell, performs a first read operation on the second memory cell,...  
WO/2018/057717A1
Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, composition of matter, and/or user interface adapted for and/or resulting from, and/or a method and/or machine-readable medium comprising machine-...  
WO/2018/055171A1
A method of erasing data using a file-based protocol from a data storage apparatus for repurposing, reallocation to a new user or retirement of the data storage apparatus, the data storage apparatus comprising a memory using a file-based...  
WO/2018/057896A1
Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows a...  
WO/2018/051140A1
A method of combining data, the method comprising: receiving video data, the video data corresponding to recorded video having a video duration determined by a user; selecting backing audio data, the backing audio data corresponding to b...  
WO/2018/052688A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold vo...  
WO/2018/052667A1
Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, respon...  
WO/2018/052596A1
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data...  
WO/2018/053413A1
In embodiments of the present disclosure improved capabilities are described for an asset intelligence platform for organizing information collected and stored on or with respect to large fleets of asset, such as used in connection with ...  
WO/2018/052697A1
A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory ce...  
WO/2018/052561A1
Techniques are provided for video summarization, based on speaker segmentation and clustering, to identify persons and scenes of interest. A methodology implementing the techniques according to an embodiment includes extracting audio con...  
WO/2018/051931A1
In order to provide a highly reliable crossbar circuit that enables salvation of reversal of the resistive state of a resistance variable element, this semiconductor device has a configuration obtained by parallelly arranging two unit el...  
WO/2018/050960A1
A method comprising: obtaining a first clean signal (S1) and a first processed signal (S4) dependent upon audio input (24) at a first microphone (25); obtaining a second clean signal (S2) and a second processed signal (S3) dependent upon...  
WO/2018/052696A1
Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in anal...  
WO/2018/051357A1
A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels ...  
WO/2018/051598A1
A magnet structure (1) is provided with a first magnet unit (10) and a second magnet unit (20). The first magnet unit (10) is formed with a first magnet fixing portion (12) which includes a first surface (12a) and a first magnet (14) hav...  
WO/2018/051307A1
The present invention relates to frameworks and methodologies configured to enable support and delivery of a multimedia messaging interface, including (but not limited to) automated content generation and classification, content search a...  
WO/2018/053181A1
Systems and methods in accordance with embodiments of the invention implement optical systems incorporating lens elements formed separately and subsequently bonded to low co¬¨ efficient of thermal expansion substrates. Optical systems in...  
WO/2018/048682A1
The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre- charge circuit for pre-charging a bit line during a pre-ch...  
WO/2018/047736A1
A magneto-resistive device 100 is characterized in comprising first magneto-resistive elements 101a, 101b, a second magneto-resistive element 101c, a first port 109a, a second port 109b, a signal line 107, and a direct current input term...  
WO/2018/048607A1
Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache ent...  
WO/2018/048490A1
Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain th...  
WO/2018/045773A1
A method for updating data in a memory used for electrical compensation and a data updating apparatus, the method for updating data comprising: writing a number of a currently-updated block or a predetermined value into a nonvolatile mem...  
WO/2018/047558A1
The present invention implements a structure capable of reproducibly recording MPEG Media Transport (MMT) format data into a recording medium as BDAV or SPAV format data. The MMT format data is input via broadcast waves and so forth and ...  
WO/2018/048608A1
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another me...  
WO/2018/046075A1
According to the invention, a heat assisted magnetic recording disk drive is provided which comprises a magnetic recording medium (1) with a heat sink layer (4), characterized in that the heat sink layer (4) comprises at least a material...  
WO/2018/046682A1
The present invention relates to a device (100) for selecting a storage cell (310), the device comprising a first electrode (1), a second electrode (2) and an oxide layer (3) disposed between the first electrode and the second electrode,...  
WO/2018/047035A1
A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is ...  
WO/2018/048576A1
A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tra...  
WO/2018/046693A1
An apparatus for managing the storage of image data captured by a plurality of image capturing means is provided. The apparatus comprises designation means configured to receive a designation of the importance of at least one of the plur...  
WO/2018/042511A1
Provided is a method for resmoothing a magnetic disk to retrieve data recorded on a damaged data disk. The method comprises: a determination step for determining the height of a bulge around the damaged surface of the magnetic disk; a gr...  
WO/2018/044510A1
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further inclu...  
WO/2018/040576A1
A video editing method, device, terminal, and computer storage medium. The editing method comprises: determining a location to be edited corresponding to an audio to be edited (S101); acquiring an adjusted audio corresponding to the loca...  
WO/2018/041885A1
The invention relates to a device for controlling the refresh cycles of data stored in a non-volatile memory. The device comprises a temperature sensor capable of measuring the temperature of at least one non-volatile memory and of deliv...  
WO/2018/044755A1
Fuse state sensing circuits, devices and methods. In some embodiments, a fuse state sensing circuit can include an enable block configured to enable a flow of a fuse current resulting from a supply voltage to a fuse element upon receipt ...  

Matches 551 - 600 out of 855,772