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Matches 551 - 600 out of 845,503

Document Document Title
WO/2016/154824A1
Proposed is a resistor-capacitor reinforcement-based memory cell of a static random access memory, comprising a latch circuit and a bit selection circuit. The latch circuit is composed of two PMOS transistors P1 and P2, two NMOS transist...  
WO/2016/157860A1
A video playback device is provided which, from recorded programs, enables a user to select and playback a desired program with relatively little effort. A user interface generation unit of the video playback device generates multiple se...  
WO/2016/155410A1
An RRAM storage subarray structure, and reading and writing methods therefor. The RRAM subarray structure comprises a main array and a reference array. The main array comprises n rows and m columns of memory cells, and the reference arra...  
WO/2016/158554A1
HDR images and SDR images are combined and stored in content having individual segment regions comprising selection/reproduction data that corresponds to a reproduction path. HDR images and SDR images having embedded identification marks...  
WO/2016/160146A1
Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cel...  
WO/2016/157858A1
A video playback device is provided which, from recorded programs, enables a user to select and playback a desired program with relatively little effort. A user interface generation unit of the video playback device generates multiple se...  
WO/2016/154825A1
Proposed is a DICE structure-based storage unit of a static random access memory, comprising a redundant information latch circuit and a redundant selection circuit. The redundant information latch circuit is composed of four MOS tubes a...  
WO/2016/158865A1
This magnetoresistive effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer sandwiched between the first and second ferromagnetic metal layers, wherein: the tunnel barrier la...  
WO/2016/161046A1
Systems and methods, and computer readable media bearing instructions for carrying out methods of capturing notes from passive recording of an ongoing content stream are presented. Passive recording comprises temporarily recording the mo...  
WO/2016/158426A1
Provided is a ferritic stainless steel sheet which exhibits excellent cleanability, anti-glare properties, and hydrophilicity. In this ferritic stainless steel sheet, which is temper rolled using a dull roll after being subjected to fini...  
WO/2016/158923A1
This magnetoresistive effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer sandwiched between the first and second ferromagnetic metal layers, wherein: the tunnel barrier la...  
WO/2016/160071A1
Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on t...  
WO/2016/156918A1
A method and system for managing a transmission buffer memory at a base station in a wireless communication system, the base station having a plurality of cells, the memory being circular and shared among the cells so that memory fragmen...  
WO/2016/160669A1
Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semi...  
WO/2016/161229A1
Systems and methods, and computer readable media bearing instructions for carrying out methods of capturing notes from passive recording of an ongoing content stream and annotating the note with the identity of one or more persons are pr...  
WO/2016/155362A1
A play control method and terminal. The method comprises: detecting a first sliding track inputted in a device list interface (S101); obtaining a device identifier included in a device identifier area through which the first sliding trac...  
WO/2016/154855A1
Disclosed in the present invention is a method of expanding a function of an Android standard multimedia player. The method comprises: registering on an Android operating system an expanded multimedia player different from the Android st...  
WO/2016/155946A1
A method of communicating data imperceptibly in an audio signal. The method comprises, for each sub-band of the audio signal, identifying the tone in that sub-band having the highest amplitude. An audio code comprising the data to be com...  
WO/2016/161231A1
Systems and methods, and computer-readable media bearing instructions for carrying out methods of capturing notes from passive recording of an ongoing content stream and assigning a task to a target user regarding the captured/generated ...  
WO/2016/157265A1
Provided is a reproduction method suited to a reproduction device for reproducing a system stream file including coded video information. The system stream file includes: a first section in which first data units decodable with a first d...  
WO/2016/158230A1
Provided is a skyrmion generation method in which the power consumed during generation of skyrmions can be reduced. In this skyrmion generation method, an electric field is locally applied to an insulating magnetic body 12 having a chira...  
WO/2016/161232A1
Systems and methods, and computer-readable media bearing instructions for carrying out methods of capturing notes from passive recording of an ongoing content stream and associating visual content (e.g., images and video) with the note a...  
WO/2016/158910A1
This magnetoresistive effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer sandwiched between the first and second ferromagnetic metal layers, wherein: the tunnel barrier la...  
WO/2016/160177A1
Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating...  
WO/2016/160578A1
An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. Wh...  
WO/2016/158926A1
This magnetoresistive effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer sandwiched between the first and second ferromagnetic metal layers, wherein: the tunnel barrier la...  
WO/2016/154927A1
Disclosed is a fixing structure (100), comprising a supporting member (12) for bearing a solid state disk (200), a guiding member (13) for guiding the solid state disk (200) to slide in a predetermined direction being provided on the sup...  
WO/2016/157412A1
This semiconductor device is provided with an SRAM circuit. The SRAM circuit includes: a memory array (11) wherein a plurality of memory cells (MC) are disposed in matrix; ground wiring (ARVSS) to which the memory cells (MC) are connecte...  
WO/2016/155057A1
A shift register circuit (1), comprising M levels of shift register sub-circuits. An Nth level shift register sub-circuit (10) comprises an Nth level control signal input end (G(N-1)), a clock signal output control circuit (110), a buffe...  
WO/2016/158529A1
Proposed are a non-volatile SRAM memory cell and a non-volatile semiconductor storage device. In a non-volatile semiconductor storage device (1), the voltage required for a program operation for writing SRAM data to a non-volatile memory...  
WO/2016/154826A1
Provided is a storage unit of a static random access memory based on resistance reinforcement, comprising a latch circuit and a bit selection circuit, wherein the latch circuit is composed of two PMOS transistors P1 and P2, two NMOS tran...  
WO/2016/159017A1
A magnetic resistance effect element (100) is provided with: a bias layer (11) containing an antiferromagnetic body, the bias layer (11) being shaped so as to extend in a first direction; a record layer (12) comprising a magnetic body, t...  
WO/2016/154144A1
A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase ...  
WO/2016/150089A1
A shift register, a gate electrode drive circuit, a display panel, and a display apparatus, the shift register comprising: an input module (01), used for outputting a signal of a signal input terminal (Input) to a first node (P1); a rese...  
WO/2016/150624A1
As a potential format for next-generation audio, techniques for embedding digital watermarks in the Higher Order Ambisonics (HOA) representation of a sound field have been proposed. The inventive embedding method is adapted for watermark...  
WO/2016/153377A1
´╗┐An improved technique for storing trace data involves storing software operation debug trace information in a buffer memory rather than in a log file in the main memory, and after completion of the software operation either (1) deleti...  
WO/2016/153513A1
A code comparator has a processor and a memristor array having a plurality of row lines, a plurality of column lines, and a plurality of memristors. The processor is to assign a row voltage value to the row lines, where the row voltage v...  
WO/2016/153654A1
Embodiments of the present disclosure are directed towards techniques and configurations for providing an apparatus comprising a memory array, to which bias voltage may be provided to reduce leakage current. In one embodiment, the appara...  
WO/2016/154083A1
A method of operating a storage controller is provided. The method includes receiving first host data traffic from a host, for storage in a first partition within a storage system, the first host data traffic formatted for storage in a f...  
WO/2016/153560A1
Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second da...  
WO/2016/153648A1
In one embodiment, a memory such as a dynamic random access memory employs charge boosting to bitcells prior to sensing charge levels in the storage nodes of the bitcells. It is believed that such an arrangement may be employed to improv...  
WO/2016/153633A1
Described is an apparatus which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cel...  
WO/2016/153634A1
Embodiments of the present disclosure describe chalcogenide glass compositions and chalcogenide switch devices (CSD.) The compositions generally may include 3% to 15%, silicon, 8% to 16% germanium in, greater than 45% selenium, and 20% t...  
WO/2016/153778A1
In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a dr...  
WO/2016/154597A1
A three-dimensional double-density NAND flash memory device is disclosed. In one aspect, an apparatus includes a three dimensional stacked configuration of word line layers separated by insulating layers. The stacked configuration includ...  
WO/2016/154078A1
A method of operating a storage controller is provided. The method includes receiving host data for storage within a storage system, the storage system configured as a plurality of sequentially numbered data blocks, each comprising a plu...  
WO/2016/154298A1
A system and method for automatically interpreting EEG signals is described. In certain aspects, the system and method use a statistical model trained to automatically interpret EEGs using a three-level decision-making process in which e...  
WO/2016/153965A1
Systems and method for controlling the programming of a one-time programmable (OTP) memory are disclosed. The systems and methods include an OTP memory array comprising an array organized in lines of n+1 bit, wherein n is an integer numb...  
WO/2016/154079A1
A method of operating a storage controller including (a) receiving host data from a host, for storage within a partition in the storage system, and (b) determining a quantity of error correction code levels based on at least one partitio...  
WO/2016/154449A1
In described examples, a split-gate flash memory cell (cell) includes a semiconductor surface (205a). A first control gate (CG) (230) on a first floating gate (FG) (210) and a second CG (240) on a second FG (220) are each on a tunnel gat...  

Matches 551 - 600 out of 845,503