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Patent Searching and Data


Matches 551 - 600 out of 858,792

Document Document Title
WO/2019/059022A1
The present technology pertains to a reproduction device, a reproduction method, a program, and a recording medium, in which display at the start of reproduction of an HDR video stream can be made stable. In a case where: reproducible co...  
WO/2019/056833A1
Provided are a shift register unit, scan driving circuit, array substrate, and display device, said shift register unit comprising: an input circuit (11), used for setting a first node (PU) to a valid level when an input terminal (IN) is...  
WO/2019/056282A1
A mobile hard disk capable of displaying storage capacity and a working method therefor. The mobile hard disk comprises a housing (1), a USB data interface (2) is provided on a side face of the housing (1), and a hard disk motherboard (3...  
WO/2019/060868A1
A system for cleaning a media transport device includes a cleaning substrate sized and configured to fit within at least a portion of a media travel pathway of the transport device. The cleaning substrate includes scarifying holes that s...  
WO/2019/060573A1
A method of detecting random telegraph noise defects in a memory includes initializing a first bit cell of the memory to a first value and reading the first value from the first bit cell. The method also includes writing a second value t...  
WO/2019/060120A1
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first stat...  
WO/2019/059591A1
A semiconductor memory device is disclosed. The semiconductor memory device comprises: a first circuit unit including a third PMOS transistor and a first inverter, which includes a first NMOS transistor and a first PMOS transistor; a sec...  
WO/2019/055182A1
A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate dispos...  
WO/2019/051861A1
A mixed flash memory read/write method and a mixed read/write flash memory. In the mixed flash memory read/write method, operations of the following four storage modes are mixed: single-level storage, multi-level storage, triple-level st...  
WO/2019/054495A1
The purpose of the present invention is to provide a memory circuit device that enables the circuit to be downscaled. The memory circuit device is provided with: multiple memory cells 11, each comprising a variable resistance memory comp...  
WO/2019/054434A1
A failure sign detection device 40 is provided with: an issuing unit 41 that issues an access request for inspection of a storage device 50 at a prescribed first timing, and also at a second timing later than the first timing; a collecti...  
WO/2019/025864A3
The present disclosure includes distributed processors and methods for compiling code for executed by the distributed processors. In one implementation, a distributed processor may include a substrate; a memory array disposed on the subs...  
WO/2019/052061A1
A low-power consumption dual in-line memory, and an enhanced driving method therefor. The memory has a pluggable dual in-line structure and is compatible with a DDR internal memory interface. The memory has the following pin assignment b...  
WO/2019/055179A1
This disclosure provides systems, methods, and apparatus, including computer programs encoded on computer storage media, for network communication when recording audio and video (A/V) of a subject. In one aspect, a device may determine o...  
WO/2019/055935A1
A dynamic error introduced by track-and-hold circuits can be reduced by using an input signal derivative to perform linear extrapolation during the hold period, allowing the output of the track-and-hold circuit to provide improved perfor...  
WO/2019/055105A1
A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and...  
WO/2019/054001A1
A nonvolatile storage device according to the present invention is provided with: a variable resistance element (10) comprising a first electrode (2), a second electrode (4), and a variable resistance layer (3) the resistance value of wh...  
WO/2019/054148A1
A fluorine-containing ether compound which is represented by R1-R2-CH2-R3-CH2-R4-R5. (In the formula, R3 represents a perfluoropolyether chain; each of R1 and R5 independently represents an optionally substituted alkyl group, an organic ...  
WO/2019/055827A1
Disclosed are systems, devices, and processes to create a successful and effective personal video commercial through the use of one or more scripts, timecode commands, storyboarding, teleprompting displays, analyzers directed to static d...  
WO/2019/053917A1
A brightness characteristic generation method including: a first determination step (S32) for determining, for each of a plurality of frames constituting a moving image, a value obtained by dividing the number of pixels, among a pluralit...  
WO/2019/055074A1
A spin orbit torque magnetoresistive random access memory (SOT MRAM) cell includes a magnetic tunnel junction that contains a free layer having two bi-stable magnetization directions, a reference magnetic layer having a fixed magnetizati...  
WO/2019/049686A1
A combining weight coefficient used in neural network computation is stored in a memory array (20), a word line (22) corresponding to the input data of a neural network is driven by a word line drive circuit (24), and a bit line to which...  
WO/2019/049741A1
A neural network arithmetic circuit for outputting output data (y) in accordance with the results of a multiply-add operation performed on input data (x0-xn) and connection weight coefficients (w0-wn), wherein the neural network arithmet...  
WO/2019/047489A1
The present invention belongs to the technical field of ferroelectric memories. A ferroelectric memory integrated circuit provided in the present invention comprises: a ferroelectric memory array having a memory unit array formed on a fe...  
WO/2019/050848A1
Bi-stable static random access memory (SRAM) bit cells formed from III- V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate (202), a first well layer (2...  
WO/2019/049385A1
Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplif...  
WO/2019/051354A1
Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as me...  
WO/2019/049980A1
In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfigu...  
WO/2019/050867A1
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a fi...  
WO/2019/050625A1
Numerous embodiments of circuitry for writing to and reading from resistive random access memory cells are disclosed. Various architectures and layouts for an array of resistive access memory cells also are disclosed.  
WO/2019/050117A1
The present invention relates to a device and a method for producing a multimedia book. The present invention provides a device and a method for producing multimedia book content, whereby recorded data for content on the respective pages...  
WO/2019/048967A1
Provided is a storage device in which the parasitic capacitance of a bit line has been reduced. The storage device comprises a sense amplifier that is electrically connected to a bit line, and a memory cell array that is layered upon the...  
WO/2019/049842A1
Provided is a neural network computation circuit capable of outputting output data according to the result of a multiply-accumulate operation performed on input data and connection weight coefficients, said circuit comprising a computati...  
WO/2019/049585A1
Provided is a fluorinated ether compound represented by formula (1). (1): R1-R2-CH2-R3-CH2-R4 (In the formula (1), R1 is an alkyl group optionally having a substituent, R2 is a divalent linking group linked to R1 via etheric oxygen, R3 i...  
WO/2019/048979A1
Provided is electronic equipment having a semiconductor device capable of intermittent operation. The electronic equipment has a semiconductor device, and the semiconductor device has a current mirror circuit, a bias circuit and first th...  
WO/2019/049013A1
Provided is a novel semiconductor device. The semiconductor device comprises a plurality of cell arrays and a plurality of peripheral circuits, wherein each cell array has a plurality of memory cells; each peripheral circuit has a first ...  
WO/2019/051446A1
Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessib...  
WO/2019/049654A1
A neural network computation circuit comprising an in-area word line multiple selection circuit for logically segmenting a plurality of word lines of a memory array (10) into a plurality of word line areas and making a given word line se...  
WO/2019/045921A1
Methods of operating memory, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of the memory, programming additional data to the particular me...  
WO/2019/045793A1
A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address ...  
WO/2019/045682A1
Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electr...  
WO/2019/042173A1
A shift register unit and a driving method thereof, an array substrate, and a display device in the field of displays. The shift register unit comprises: a shift register module (11) configured to provide a signal at a first scan output ...  
WO/2019/045792A1
A memory device (10) may include one or more memory banks (12) that store data and one or more input buffers (50). The input buffers (50) may receive command address signals to access the one or more memory banks (12). The memory device ...  
WO/2019/044156A1
Provided is an information processing system that reproduces a write to a notebook together with the state of being written to the notebook and thereby facilitates understanding of the written content of the notebook. For this purpose, a...  
WO/2019/042189A1
A shift register circuit, a driving method, a gate drive circuit, and a display device are provided. The shift register circuit comprises a clock signal adjustment circuit (13) and a self-controlled conduction circuit (14). The clock sig...  
WO/2019/045937A1
Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measur...  
WO/2019/046524A1
Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modifi...  
WO/2019/046050A1
Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a tr...  
WO/2019/044021A1
The imaging device (100) is provided with: a selector (115, 120) for selecting sound signals for a preset number of channels; and a control unit. During recording of the sound signals, when the number of channels is set to two, the contr...  
WO/2019/041827A1
A shift register unit for a gate driver circuit (GOA), a gate driver circuit comprising the shift register unit, and a driving method applied to the shift register unit. The shift register unit comprises: an input sub-circuit (110), conf...  

Matches 551 - 600 out of 858,792