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Matches 1 - 50 out of 4,870

Document Document Title
WO/2018/089121A2
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/052982A3
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may...  
WO/2017/146833A2
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/146833A3
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/048419A1
Systems and methods for dividing input clock signals (CLKin) by programmable divide ratios (N) can produce output clock signals (CLKdiv) with the delay from the input clock signal to the output clock signal independent of the value of th...  
WO/2016/187333A1
Systems and techniques are provided for a multichannel waveform synthesis engine. A phase counter module counts to a value corresponding to a number of phases available, outputs a phase counter value indicating a current phase, and reset...  
WO/2016/089291A1
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...  
WO/2016/089292A1
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...  
WO/2016/089275A1
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...  
WO/2016/074350A1
The present invention provides a burr removing method and apparatus for an optical signal loss signal. The present invention adopts the technical solution of: when detecting that an online signal output by an optical module changes from ...  
WO/2016/076798A1
A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the trans...  
WO/2016/037118A1
In described examples of providing multiple clock frequencies for an integrated circuit having a plurality of modules, a reference clock signal (fin) is frequency division processed (401) to generate sub-divider outputs of fin divided by...  
WO/2016/007552A1
A circuit (100) includes an amplifier output stage (124, 164) that includes a high switch (134, 174) and a low switch (136, 176) that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response t...  
WO/2015/116813A1
A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeedi...  
WO/2015/112609A1
A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a det...  
WO/2015/065683A1
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...  
WO/2014/209715A1
A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b)...  
WO/2014/202230A1
The present invention relates to an apparatus and a method for generating RF signals, the pulse width and pulse position of which are modulated. The apparatus comprises a digital device (2, 3) which is intended to generate different phas...  
WO/2014/164376A1
A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives...  
WO/2014/095792A1
A synchronizer circuit 200 comprises a first flip-flop operated with a first clock signal C1, the first flip-flop being configured to read a data item at a first sampling point correlating with a first edge of a first edge type of the fi...  
WO/2014/066402A1
In various embodiments, an integrated circuit is disclosed. In one embodiments, the integrated circuit comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area com...  
WO/2014/063316A1
The present invention discloses a pulse frequency measurement device and method and a control system, the device including: a hardware counter configured to perform a counting operation on an input pulse sequence to output a counting res...  
WO/2014/043339A1
A divider (200) apparatus includes latches ( 202-1,202-2) that are coupled in series with one another in a ring configuration. Each latch includes a tri- state inverter (Q9-1Q12), a first resistor-capacitor network (R1, C1), and a second...  
WO/2013/185960A3
The invention relates to a digital sensing circuit (100) for a secondary clock signal (204) to be monitored for clock failure with the aid of a primary clock signal (202), comprising a flip-flop (102) which has a clock input (108), a dat...  
WO/2013/185960A2
The invention relates to a digital sensing circuit (100) for a secondary clock signal (204) to be monitored for clock failure with the aid of a primary clock signal (202), comprising a flip-flop (102) which has a clock input (108), a dat...  
WO/2013/179089A1
A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged t...  
WO/2013/155352A1
A frequency divider circuit having two stages of transistors has improved performance at low supply voltages. The circuit may include cross-coupled PMOS (112a, 112b) and NMOS transistors (114a, 114b), in which the input signal to be freq...  
WO/2013/128334A1
There is provided a method of controlling a CPRI monitor port of a remote radio equipment following a powering cycle. Access to the CPRI monitor port is first detected. An absence timer decrementing process is started when the CPRI monit...  
WO/2013/098127A1
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-...  
WO/2013/082611A3
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a comp...  
WO/2013/060134A1
The present invention provides a time-resolved single-photon or ultra-weak light multi-dimensional imaging system and method. In one aspect, to achieve coarse time resolution, the present invention provides a time-resolved single-photon ...  
WO/2013/057060A1
A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an ...  
WO/2013/048525A1
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division...  
WO/2012/161003A1
A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number o...  
WO/2012/112671A3
A single stage divider is adapted to operate at very high frequencies. A differential input signal (INP, INM) (for example, with about 120GHz frequency) is divided by divider (100) to provide a differential output signal (OUTP, OUTM) wit...  
WO/2012/112671A2
A single stage divider is adapted to operate at very high frequencies. A differential input signal (INP, INM) (for example, with about 120GHz frequency) is divided by divider (100) to provide a differential output signal (OUTP, OUTM) wit...  
WO/2012/042044A8
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMO...  
WO/2012/042044A2
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMO...  
WO/2012/042044A3
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMO...  
WO/2012/041917A2
A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an...  
WO/2012/041917A3
A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an...  
WO/2012/038882A9
A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory contro...  
WO/2012/038882A1
A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory contro...  
WO/2012/025191A1
The invention relates to a method for measuring a period of time between a first event and a second event using a hardware counter (2) and a software counter (3). The invention also relates to a digital counter (1) using such a method.  
WO/2012/014013A3
The invention pertains to a latch circuit (10) comprising a sensing arrangement (12) with one or more sensing transistors (T 1, T 2 ) adapted to sense an input signal (D, D n ) and to provide a first signal based on the sensed input sign...  
WO/2012/003480A3
A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second porti...  
WO/2011/130052A1
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment...  
WO/2011/103103A1
A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circ...  
WO/2011/100032A3
Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. In a described apparatus, a preconditioner 204 has logic 206 mapped to o...  
WO/2011/100032A8
Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. In a described apparatus, a preconditioner 204 has logic 206 mapped to o...  

Matches 1 - 50 out of 4,870