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Document Title 
JP2003124802A 
To provide a frequency divider whose highest frequencydivision frequency is high and which can operate fast.A 1st LC resonant circuit, a 2nd LC resonant circuit, a 3rd LC resonant circuit, and a 4th LC resonant circuit which have resona...

JP2003110421A 
To realize a frequency divider capable of increasing an operation frequency to a counter operation frequency inside a variable frequency divider.A frequency dividing data generating section 12 consists of ring counters 121124, and data ...

JP2003513582A 
(57) It is indicated together with the sequence method containing the summary modulos 10, 12, 14, and 22 which the Gray code counter (AP1, AP4, AP5, AP6) which is not the number of ベキ of 2 is using. Each counter contains the register...

JP3388527B2 
PURPOSE: To optimize phase noise and frequency switchover at the time of using a synthesizer capable of varying the frequency division ratio in a oneNth frequency divider. CONSTITUTION: The synthesizer is provided with a variable freque...

JP3389292B2 
PURPOSE: To obtain the frequency divider circuit which can reduce a chip area. CONSTITUTION: 2n+11 pieces of signal generating circuits 14 for generating a 1/2 frequency dividing signal or a buffer signal of an input signal in accordanc...

JP2003087113A 
To provide a frequency divider circuit for reducing power consumption and facilitating timing and a PLL provided with the frequency divider circuit.This PLL is provided with a phase comparator circuit 103 for inputting a reference clock ...

JP2003069421A 
To provide a counter timing control circuit that can control a synchronization operation of counters in a control system and a system to be controlled at a low speed.A timing generator 14 outputs timing signals (111, 112), (121, 122) and...

JP2003069420A 
To provide a counter circuit that can reduce the power consumption while maintaining the operating frequency equal to that of a conventional synchronous counter.The counter circuit 100 comprises a synchronous counter section 110, an asyn...

JP2003069419A 
To provide a counter circuit that can revise a count for carrying with a simple configuration and count a plurality of kinds of cardinal numbers.A counter 10 comprises carrying circuits 141 to 14j1 including JKFF circuits 121 to 12k and...

JP3382329B2 

JP3380651B2 

JP3381175B2 

JP2003506909A 
(57) If summary book invention is said roughly, it will realize distribution of a signal within PLL using two or more モデュラスプリ scalers depended on making モデュラス which carries out dividing interleave. Within the give...

JP2003506954A 
(57) Summary book invention relates to the frequency synthesizer which works according to the principle of fraction frequency synthesis. This synthesizer consists of an integer frequency divider which can be adjusted, and a control devic...

JP2003037495A 
To provide a synchronous counter that can enable highspeed processing of a multibit counter. The synchronous counter is provided with first to nth count circuits, first to nth decoding means, first to (n1)th timing adjustment means...

JP3372858B2 

JP3370256B2 

JP2003023351A 
To provide a noninteger frequency divider and a fractional N frequency synthesizer in which noises through a power source caused by the operating current of an accumulator are reduced and a high C/N and high speed frequency switching ca...

JP3368349B2 
PURPOSE: To decrease the number of input circuits against the input number and also to simplify the circuit constitution together with reduction of its size and cost by providing a circuit which switches and outputs plural low speed inpu...

JP3369746B2 

JP2002368604A 
To provide a shift register circuit that can prevent attenuation of a signal voltage, without the having to install a capacitor and cope with miniaturization of transistors(TRs) and the circuit configuration adopting a lower power supply...

JP3354597B2 

JP2002344308A 
To reduce the power consumption and the circuit scale of an odd number frequency divider having an output signal duty of 1/2.A plurality of masterslave D flip flops(MSDFF) are connected in cascade and operated synchronously on the same...

JP3350005B2 

JP3350076B2 

JP3349347B2 

JP3350337B2 

JP3347957B2 

JP3349170B2 
PURPOSE: To ensure a stable and high speed operation of a CMOS variable frequency divider circuit even with the power voltage of a low level by performing the odd division necessary for a variable frequency dividing operation and the div...

JP3343918B2 

JP2002325041A 
To provide a method and a circuit for converting a code while reducing the circuit scale.A 2N bit signal comprising a basic N bit signal and a signal obtained by inverting each of N bits is inputted and only 1 bit is inverted to output 2...

JP3340142B2 

JP3339428B2 
To provide a dynamic frequency divider with resetting function which can be initialized in arbitrary timing. This dynamic frequency divider when receiving a reset signal from its reset terminal sets a node 118 to a high level by a P chan...

JP2002314405A 
To provide a PLL circuit adopting pulse swallower system the power consumption of which can be reduced.The PLL circuit is provided with a swallower counter control circuit 5 that controls counts of a swallower counter 4, a program counte...

JP2002314404A 
To provide a frequency divider with a wide operable frequency range for stable 1/(2n+1) frequency division (n is an integer of 1 or over) even at a low speed operation or a high speed operation when a phase difference between the two out...

JP3336054B2 

JP2002305443A 
To provide a timer circuit producing an output signal having a stabilized frequency, while reducing power consumption.The timer circuit 10 comprises a high stability oscillator 21, a counter 22, and a frequency division value control cir...

JP2002305440A 
To provide a programmable fractional division of frequency for performing fractional frequency division of a digital signal capable of improving solution, and realizing resolution step of 1/N (N is a nonzero natural integer).At conducti...

JP2002271190A 
To solve the problem in which a clock voltage is usually set half as large a s the operating voltage, so as to increase gm of an Ntype or a Ptype MOS transistor to a maximum, when the DFF circuit of a dividing circuit is driven by the ...

JP2002271189A 
To provide a counter circuit and a counting method capable of operating at a high speed and successively executing binary counting operations.A counting circuit is equipped with a first, a second, a third, and a fourth bit generating cir...

JP2002530919A 
(57) A summary digital aftergeneration machine is equipped with the 1st input from which a single phase clock signal is received, the 2nd input that receives the signal in which the delay for telling cell delay is possible, and the outp...

JP2002229668A 
To provide a register device capable of reducing a delay time of a clock signal for highspeed operation and capable of restricting the power consumption and an influence of the noise even in the case of controlling a buffer and a clock ...

JP2002232289A 
To provide a gray code counter, with which skip counting is enabled and the number of bit transitions in skip counting is two at all the time.This gray code counter is provided with a gray code counter 2 in the configuration of 5 bits fo...

JP2002217689A 
To compensate a frequency fluctuation caused by a variation of an RC oscillation circuit, etc., and to realize an accurate operation clock.There are provided an RC oscillator 1 (10) including resistors and capacitors, a counter (20) coun...

JP2002217710A 
To provide an F/F+1 prescaler that is stably in operation by a low consumed current at a low power supply voltage.The size of MOS transistors(TRs) (50, 51) for frequency division ratio switching is selected greater than that of other dif...

JP2002217711A 
To provide a prescaler that can sufficiently ensure the margin time of a frequency division ratio switching operation against malfunction.A switching signal generating section P selects output timing of a frequency division ratio switchi...

JP2002215118A 
To obtain a display device provided with a dynamic ratioless shift register operating stably and permitting to increase a degree of freedom for design.This is a dynamic ratioless shift register provided with thin film transistors of whic...

JP3309361B2 
PURPOSE: To enable the designing of an efficient highspeed counter structure used for measuring an arbitrary range. CONSTITUTION: The highspeed counter is a functional block structure flexibly connected by a bus structure. A set of ind...

JP2002208841A 
To provide a dynamic flipflop where a floating signal will not make the voltage held to fall below the substrate voltage level in a Ptype semiconductor substrate and will not make a voltage that exceeds the substrate voltage level in a...

JP3305975B2 
To enhance the operating speed, by counting up or counting down synchronizing with clock signal from a value represented by an address outputted from an arithmetic and logic unit, and providing an output control circuit for successively ...
