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JPH10276083A |
To selectively generate the even-numbered frequency division clocks and odd-numbered frequency division clocks of a duty factor 50% practically in a simple circuit suitable for being made into an IC by validating a first logic circuit co...
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JPH10261953A |
To provide an odd number frequency division clock generating circuit which is a simple circuit suitable for circuit integration and is able to generate an add number frequency division clock whose the pulse duty cycle is substantially 50...
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JP2804421B2 |
PURPOSE: To ensure an operation of high frequency by reducing the delay of the dividing ratio switching control. CONSTITUTION: A prescaler consists of the variable dividing circuits connected in cascade to each other. The dividing ratio ...
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JPH10247850A |
To reduce a circuit configuration area with the addition of a flip-flop by adopting the configuration that one flip-flop is not added to a frequency divider of a modulator prescaler, in order to provide a frequency division number of 1/(...
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JPH10509544A |
(57) [Summary] A monolithic integrated circuit that enhances the audio performance of a personal computer is disclosed. This monolithic circuit comprises a wavetable synthesizer and a full-function stereo coding / decoding circuit (CODEC...
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JPH10242949A |
To make it possible to accurately convert the frequency of data without being influenced by the dispersion of propagation delay time in hardware. In the case of converting data DX synchronized with a certain reference clock into data DY ...
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JP2792280B2 |
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JP2790551B2 |
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JPH10207780A |
To extend the whole life of the frequency counter by reducing a difference between the rewriting frequency of a 1st storage area (level 1) and that of a 2nd storage area (level 2). An IC card 10 has an EEP ROM 1 and a control circuit 2. ...
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JP2768013B2 |
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JP2769157B2 |
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JP2770204B2 |
PURPOSE: To precisely make a lock instruction by using a phase-locked loop that has an input signal and an output signal and generating a lock detection signal in response to a relative phase of the input and output signals of the phase-...
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JP2767789B2 |
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JPH10150360A |
To obtain a window clock signal without the use of a double frequency signal in an active phase by frequency-dividing a main clock signal, generating an AND signal, and converting the AND signal into two signals whose phases are deviated...
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JPH10150361A |
To provide a comparison frequency divider and a PLL circuit that prevents malfunction of a prescaler by eliminating an input delay of a module control signal to the prescaler with respect to an output signal of the prescaler. A control c...
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JPH10145226A |
To reduce a circuit scale forming an entire circuit by inputting a signal directing the value preceding by one to the first value and a signal directing the value next to the last value by two AND gates to a flip flop circuit. A signal A...
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JPH10145346A |
To provide the data phase shift circuit by which continuity of data is secured by eliminating matching of an input phase and an output phase resulting from various cause, such as ambient temperature and secular change of the circuit. The...
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JP2758877B2 |
To reduce the number of timer registers to only one and to reduce the whole circuit scale by providing plural matching data storage circuits storing the timer values corresponding to each counter without providing a register block with a...
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JP2758994B2 |
PURPOSE: To produce a time reference signal tuned to a variable system reference signal. CONSTITUTION: An oscillator circuit 20 is tuned to the spindle index pulse of a rotary magnetic storage disk device, for example. A ring oscillator ...
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JP2758564B2 |
PURPOSE: To increase the processing speed of a frequency dividing device for frequency-dividing the standard signal with a fractional ratio having each integer of a numerator and a denominator. CONSTITUTION: The output pattern of a frequ...
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JP2757827B2 |
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JP2757631B2 |
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JPH10135821A |
To obtain the clock generating circuit with less jitter and suitable for circuit integration by switching a frequency division ratio of integers before and after a non-integer at a prescribed switching ratio so as to realize frequency di...
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JPH10135826A |
To reduce a locking up time by allowing a phase comparing means to compare the phase of a feedback signal from a frequency divider with the phase of a reference signal from a reference oscillator with a second timing different from a fir...
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JPH10117142A |
To decrease the circuit scale and to reduce the power consumption by making a phase comparison between a delay signal generated when an input signal makes a plurality of round of a delay stage and the input signal and controlling the del...
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JP2747467B2 |
PURPOSE:To attain fast processing by combining a differential amplifier circuit pair used for reading data of each of a master circuit and a slave circuit and a differential amplifier circuit pair used for holding data with a positive fe...
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JP2747697B2 |
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JP2570562Y2 |
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JP2746846B2 |
The converter includes a double-junction superconducting quantum interference device (SQUID) voltage divider circuit, a double-junction SQUID voltage selector circuit and an output circuit in which currents generated by the selected bina...
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JP2745579B2 |
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JPH10107619A |
To reduce power consumption of a flip-flop comprising the synchronous counter. When a counter update enable signal (p) becomes H, an output signal S5b of a flip-flop(FF) 5b becomes H synchronously with the trailing of a clock signal ck a...
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JP2741737B2 |
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JP2743353B2 |
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JP2740769B2 |
One output signal of a D flip-flop circuit FF2 is fed via a wiring W1 back to an input terminal of a D flip-flop circuit FF1, while one output signal of a D flip-flop circuit FF3 is fed via a wiring W2 back to another input terminal of t...
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JPH1098381A |
To prevent output signals of two counters from interfering, even when the frequencies of output signals of the two counters are identical by providing a phase control means that controls 1st and 2nd counters frequency- dividing a same si...
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JPH1094638A |
To provide a PACHINKO ball count detector by which balls are not erroneously counted even in case of ball rotating, spinning or reciprocative vibrating to occur when the PACHINKO ball passes through the detector. A coil bobbin 13 is arra...
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JPH1093427A |
To double the resolution without raising the frequency of an original oscillation signal by providing an inversion/noninversion control circuit inverting/ noninverting the original oscillation signal and a selection means validating/ inv...
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JPH1093426A |
To provide an integrated circuit counter that produces a comparatively higher count and is tested by using a comparatively small number of clock cycles at the same time. A linear feedback shift register (LFSR 101) having nbit position (Q...
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JP2568104Y2 |
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JP2568163Y2 |
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JP2733251B2 |
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JP2732571B2 |
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JP2734175B2 |
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JP2730280B2 |
A digital time base generator circuit is provided having a first phase locked loop (12) for multiplying a reference frequency (f0) by an integer amount and a second phase locked loop (22) for multiplying the reference frequency by a diff...
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JP2728719B2 |
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JP2729196B2 |
An improved, high-speed frequency divider circuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36, 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of...
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JPH1075121A |
To provide a direct digital synthesizer which outputs frequency which is the N/M times (N and M are integers) clock frequency with no periodic frequency fluctuation and without the use of a ROM. This device is provided with a digital pul...
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JPH1065538A |
To provide a frequency synthesizer in which switching between a fundamental frequency and an offset frequency is feasible, the circuit is simplified and production of an undesired circuit is prevented. A programmable divider (PD) 4 has a...
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JP2719609B2 |
A frequency divider (50) for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate (51) ...
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JP2719620B2 |
A counter cell (10) for counting either up or down by one or two includes a multiplexer section (12), an increment/decrement section (14), and a carry section (16). The multiplexer section (12) is responsive to control signals and input ...
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