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Matches 701 - 750 out of 661,464

Document Document Title
WO/2021/212399A1
A programming method for a memory device includes simultaneously starting to program a first plane and a second plane; and bypassing the first plane and keeping programming the second plane when the first plane has been programmed succes...  
WO/2021/212984A1
An on-chip measurement circuit and measurement method for low-voltage SRAM time parameters, the measurement circuit comprising a measurement control module and a time measurement module, wherein the time measurement module is connected t...  
WO/2021/216464A1
A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The compiler allocates instructions of the computer program to different groups of processing ...  
WO/2021/216842A1
Described are CMOS-compatible protonic resistive devices (e.g., processing elements and/or memory elements). In embodiments, a protonic resistive memory can be formed from a proton-sensitive metal oxide channel where the concentration of...  
WO/2021/208637A1
A manufacturing method for a semiconductor structure, comprising: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode that penetrates through the first shielding layer; forming a storage str...  
WO/2021/207916A1
The present disclosure provides a memory cell structure, a memory array structure, and a voltage bias method. The memory cell structure comprises: a substrate layer, a well layer, and a transistor. The substrate layer is used for support...  
WO/2021/211716A1
A method of analyzing instructor discourse includes recording an audio signal representing speech of the instructor during a class session, converting the audio signal to a session transcript comprising speech data for the session using ...  
WO/2021/208825A1
Provided is a photoelectric device provided with an anti-contamination apparatus; the device comprises an optical component, an optical chamber, and an anti-contamination apparatus; the optical chamber is an enclosed chamber and is used ...  
WO/2021/210475A1
A semiconductor storage device according to one embodiment of the present disclosure comprises a plurality of memory cells and a control circuit. Each memory cell includes a magnetization inversion storage element and a first switch elem...  
WO/2021/211710A1
Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the ...  
WO/2021/209858A1
Provided is a semiconductor device which can hold analog data. Two holding circuits, two bootstrap circuits, and one source follower circuit are constituted by using two capacitive elements and four transistors. Storage nodes are provide...  
WO/2021/208436A1
A memory and a memory read/write method, for use in preventing an MRAM from being easily damaged or degraded due to an excessive write current during use, and having large memory integration density. The memory comprises: a storage unit ...  
WO/2021/209829A1
A differential mixed-signal logic processor is provided.The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B.Each o...  
WO/2021/207965A1
A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at lea...  
WO/2021/211164A1
The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embo...  
WO/2021/208076A1
A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one fir...  
WO/2021/211859A1
Hardware-assisted Dynamic Random Access Memory (DRAM) row merging, including: identifying, by a memory controller, in a DRAM module, a plurality of rows storing identical data; storing, in a mapping table, data mapping one or more rows o...  
WO/2021/210598A1
The present invention provides a photocurable composition which has excellent barrier properties against both water and helium and can retain satisfactory force of adhesion to adherends. This photocurable composition comprises the foll...  
WO/2021/211780A1
A sample-and-hold circuit (210) includes a first input resistor (RP), a first transistor (MINP), a first capacitor (C1), a second resistor (R1), and a first current source device (L1). A first current terminal of the first transistor (MI...  
WO/2021/211171A1
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones, each zone comprises a plurality of erase blocks. Data is wr...  
WO/2021/211272A1
Implementations of the subject technology provide systems and methods for recording an extended reality experience in a way that allows the experience to be played back at a later time from a different viewpoint or perspective. This allo...  
WO/2021/205271A1
A system and a method are disclosed describing a mechanism for preventing recording of security sensitive media content when that content is displayed on a screen. The mechanism includes selecting two refresh rates for a display and osci...  
WO/2021/206973A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to perform at least computations on matrix operands and configured with: random access memory configur...  
WO/2021/207234A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions wi...  
WO/2021/206944A1
In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Data from the master die may ...  
WO/2021/206974A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to s...  
WO/2021/207236A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured with: a Central Processing Unit, a Deep Learning Accelerator configured to execute instructions with m...  
WO/2021/206882A1
Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write oper...  
WO/2021/206908A1
Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and ...  
WO/2021/203544A1
A GOA circuit (200) and a display panel. The GOA circuit (200) comprises a plurality of GOA units arranged in cascade, the GOA units each comprising a first GOA unit (20) and a second GOA unit (30). A virtual reset module (107) is provid...  
WO/2021/206996A1
A method of forming a tunnel layer of a magnetoresistive random-access memory (MRAM) structure includes forming a first magnesium oxide (MgO) layer by sputtering an MgO target using radio frequency (RF) power, exposing the first MgO laye...  
WO/2021/203238A1
Provided is a shift register circuit (RS), comprising: a first input sub-circuit (101), an output sub-circuit (102), and an output control sub-circuit (103), wherein under the control of a signal received at a first signal input end (IN1...  
WO/2021/206943A1
Apparatuses and methods for repairing a memory are disclosed. In some examples, the memory may be a stacked memory that includes multiple die and at least one spare die. In some examples, a die may determine it is defective and provide s...  
WO/2021/206945A1
Apparatuses and methods for providing data from stacked memory are described. The stacked memory may include multiple die. In some examples, a master die may receive data from one or more slave die. The master die may provide data from t...  
WO/2021/203895A1
A training method for a semiconductor memory and a related device, belonging to the technical field of semiconductors. Said method comprises: acquiring a stored historical training result of the semiconductor memory, the historical train...  
WO/2021/205456A1
An electronic memory block comprises phase change memory cells for memory storage and further phase change memory cells forming logic gates, to provide in-memory' data processing.  
WO/2021/207237A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructi...  
WO/2021/206095A1
An aluminum alloy substrate for magnetic disks, characterized by comprising an aluminum alloy which contains Fe that is an essential element and also contains at least one of Mn and Ni that are selective elements in which the total conte...  
WO/2021/207750A1
A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch...  
WO/2021/206903A1
Embodiments of the disclosure are drawn to apparatuses and methods for command/address tracking in memory. Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command s...  
WO/2021/206958A1
Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data tr...  
WO/2021/207050A1
A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, where...  
WO/2021/206892A1
Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, an...  
WO/2021/206097A1
Provided are: an aluminum alloy substrate for a magnetic disk; and a magnetic disk using same. The aluminum alloy substrate is composed of an aluminum alloy containing 1.0-6.5 mass% of Mg, with the remainder comprising Al and inevitable ...  
WO/2021/207404A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be configured on a local area network to receive sensor data of a person, such as a patient in a hospital or care center. T...  
WO/2021/198669A1
Systems and methods for digital watermarking at a content distribution network, CDN, node are described, whereby source data intended for at least one recipient is received from an origin server, the source data including a plurality of ...  
WO/2021/199386A1
The need for searching as to "which data stored inside a storage circuit is most similar to input information from the outside" is increasingly expanding, and there is, regarding a storage circuit, a high expectation for such a memory te...  
WO/2021/196853A1
Some of the embodiments of the present invention relate to the technical field of semiconductors. Disclosed are a memory block and a memory. The memory block comprises: one or more memory modules (100), each memory module (100) comprisin...  
WO/2021/202353A1
Advertisement preparation methods and systems are shown and disclosed. In one embodiment, the method includes reviewing metadata of an advertisement. The metadata includes duration information for the advertisement, and determining actua...  
WO/2021/198375A1
A light-emitting polymer comprising a repeat unit of formula (I): R1-R4 are each independently H or a substituent; and Ar1 and Ar2 are each independently an aromatic or heteroaromatic group selected from formulae (Ila) and (lib): The pol...  

Matches 701 - 750 out of 661,464