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WO/2023/173608A1 |
An anti-fuse memory array circuit and an operation method therefor, and a memory. The anti-fuse memory array circuit comprises: at least one anti-fuse memory array (10), the anti-fuse memory array comprising multiple anti-fuse memory cel...
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WO/2023/173259A1 |
Provided are a shift register unit and a driving method therefor, a gate driving circuit, and a display device, relating to the technical field of display. An output circuit in the shift register unit may control, on the basis of a poten...
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WO/2023/173530A1 |
A convolution operation accelerator and a convolution operation method, relating to the field of microelectronic devices. Each word line electrode connects one column of non-volatile memory cells in non-volatile memory cells arranged in ...
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WO/2023/173636A1 |
An electronic device and a driving method therefor. The electronic device comprises a sense amplifier (SA) and a voltage regulation circuit (6). The sense amplifier (SA) comprises a first P-type transistor (PM1), a second P-type transist...
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WO/2023/177864A1 |
Methods and systems for encoding digital information in nucleic acid (e.g., deoxyribonucleic acid) molecules without base-by-base synthesis, by encoding bit-value information in the presence or absence of unique nucleic acid sequences wi...
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WO/2023/175684A1 |
Provided are a convenient memory system, a control method therefor, and an information processing device. A memory system 100 according to an embodiment comprises: a non-volatile memory 2 that has memory cells capable of storing user d...
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WO/2023/173492A1 |
The present application discloses a shift register, a gate driving circuit, and a display device. According to the shift register of the present application, when a pull-up node is at a low level, a first noise reduction module is contro...
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WO/2023/174609A1 |
The invention relates to a provisioning control apparatus (140) configured to be coupled to a provisioning apparatus (160), wherein the provisioning apparatus (160) is electrically connectable with a plurality of pins of an electronic co...
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WO/2023/177531A1 |
A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through...
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WO/2023/176510A1 |
A non-volatile memory device (1) comprises: a first current mirror (8) which has a reference element (81) that is configured as a memory element capable of executing a program operation and a data element (82) that is configured as the m...
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WO/2023/173983A1 |
Disclosed in the embodiments of the present application are a storage apparatus and a related instruction delay statistical analysis method. The storage apparatus is characterized in that the storage apparatus is used for: receiving N op...
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WO/2023/172581A1 |
Methods and systems for determining past and future cycles of scenes that employ looping functions are disclosed. In one embodiment, a scene that includes a repeating segment may be created. The repeating segment may have a finite durati...
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WO/2023/170172A1 |
A resistive switching memory device comprises an active layer comprising an ionic conducting material. The active layer is disposed on a substrate. The device further comprises: a first electrode, a second electrode and optionally a firs...
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WO/2023/168817A1 |
A test method for a memory chip, a test apparatus for a memory chip, a computer readable storage medium and an electronic device, belonging to the technical field of semiconductors. The method comprises: determining a memory block corres...
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WO/2023/172398A1 |
One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, eac...
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WO/2023/169075A1 |
The present application relates to the technical field of data storage, and particularly to a read-write circuit, a read-write method, and a ferroelectric memory. The read-write circuit comprises: a sensitive amplifier, which is coupled ...
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WO/2023/172755A1 |
A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level...
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WO/2023/169420A1 |
The present invention provides a memory control system and method. The system comprises: a memory which comprises a main storage module and a built-in EEPROM; a storage controller which, in a normal mode, reads a program in the main stor...
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WO/2023/171824A1 |
A discoidal glass substrate (1) manufacturing method includes: preparing a discoidal glass blank having main surfaces (11a, 11b) and an outer circumferential edge surface (12); and projecting laser light (L) more than once around the out...
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WO/2023/168727A1 |
A repair system (100) and repair method for a semiconductor structure, and a storage medium and an electronic device. The semiconductor structure comprises a main storage area and a redundant storage area. The repair system (100) compris...
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WO/2023/170816A1 |
This magnetic array comprises: a plurality of magnetoresistance effect elements; and a pulse application device that applies a pulse to at least one of the plurality of magnetoresistance effect elements. Each of the plurality of magnetor...
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WO/2023/171683A1 |
This neural network arithmetic circuit holds a plurality of coupling weight coefficients corresponding respectively to a plurality of input data pieces, and outputs output data in accordance with the results of product-sum operations bet...
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WO/2023/168847A1 |
Provided in the present disclosure are a testing circuit and method for a memory chip. The testing circuit for a memory chip comprises: a data reading apparatus, which reads word line data stored in all repositories of a memory under tes...
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WO/2023/168806A1 |
A memory failure testing method, a memory failure testing apparatus, a computer-readable storage medium, and an electronic device. The memory failure testing method comprises: writing preset storage data into a storage array of a memory ...
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WO/2023/172757A1 |
Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whethe...
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WO/2023/171452A1 |
According to the present invention, a two-port SRAM comprises load transistors (PU1, PU2), drive transistors (PD1, PD2), access transistors (PG1, PG2), a read drive transistor (RPD), and a read access transistor (RPG). Embedded wires (11...
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WO/2023/171402A1 |
A storage device (500) according to an embodiment of the present disclosure comprises: a first memory (501) that allows data reading/writing; a second memory (502) that allows data reading/writing; a detection unit (504) that detects mag...
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WO/2023/171474A1 |
A memory controller according to an embodiment of the present disclosure is capable of controlling access to a DRAM. The memory controller comprises an RAA counter capable of counting the number of issuances of an ACT command and a comma...
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WO/2023/164911A1 |
Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact cou...
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WO/2023/167805A1 |
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. I...
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WO/2023/165058A1 |
The present disclosure provides a method and apparatus for implementing mirror image storage of a memory model, and a storage medium, and relates to artificial intelligence chips, intelligent voice, and other artificial intelligence fiel...
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WO/2023/164827A1 |
The present disclosure provides an SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a firs...
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WO/2023/166376A1 |
Provided is a novel semiconductor device. In this semiconductor device, a first circuit is electrically connected to a second circuit via a first wire; the first circuit is electrically connected to a fourth circuit via a third wire and ...
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WO/2023/165981A1 |
According to various aspects, a memristive crossbar array is provided including: first control lines and second control lines in a crossbar configuration defining a plurality of cross-point regions, a memristive material portion disposed...
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WO/2023/165002A1 |
The present disclosure relates to the field of semiconductor circuit design, in particular to a data writing circuit, a data writing method, and a memory. The data writing circuit comprises: a delay generation module, for generating, on ...
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WO/2023/167244A1 |
The present invention utilizes an electric characteristic due to an electrochemical reaction corresponding to an environmental factor. An interconnection structure according to an embodiment of the present disclosure electrically connect...
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WO/2023/167681A1 |
A memory-testing circuit in a circuit comprises: a test controller; a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an o...
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WO/2023/165440A1 |
The present disclosure provides a programming method, a memory device and a memory system. The method includes, based on coupling offsets, dividing target programmed states into N groups, each group corresponding to a different first pro...
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WO/2023/165014A1 |
Provided in the present application are a programmable circuit, an integrated circuit and an electronic device. The programmable circuit comprises: a signal conversion module, which converts a parallel signal input by an external circuit...
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WO/2023/165729A1 |
A memory and routing module (100) includes a substrate (170) and a connection component (160). The connection component (160) is attached to the substrate (170) and includes multiple pins (161) that connect the module (100) to a correspo...
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WO/2023/168085A1 |
Technologies include systems, devices, and methods to write, store, read, and perform computation of digital information using nucleic acid molecules (e.g., DNA). The technologies include, for example, a device including one or more indi...
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WO/2023/165003A1 |
The present disclosure relates to the field of semiconductor circuit design, and relates in particular to a data readout circuit, a data readout method and a memory. The method comprises: a delay generation module generates, on the basis...
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WO/2023/165026A1 |
Embodiments of the present invention provide a refresh circuit, a memory, and a refreshing method. The refresh circuit comprises: a refresh counter, configured to output an address signal by means of a plurality of address pins; an addre...
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WO/2023/166138A1 |
An image processing device is provided. The image processing device includes interface circuitry configured to receive first image data representing a first image exhibiting a first aspect ratio smaller than one. The first image is a pho...
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WO/2023/167115A1 |
In modern computing, the reference for calculating storage capacity is bits, the number of transistors (elements) that become a node, namely, the number of bits is a unit of a modern information communication quantity. On the contrary, a...
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WO/2023/167728A1 |
A computing device is provided. The computing device may include a first camera configured to capture a primary image sequence of a scene, and a second camera configured to substantially concurrently capture a secondary image sequence of...
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WO/2023/165044A1 |
Provided in the present disclosure are a memory detection method, circuit, apparatus and device, and a storage medium. The memory detection method comprises: writing test data into at least some storage units of a memory; turning on word...
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WO/2023/165934A1 |
Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage d...
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WO/2023/162804A1 |
A memory device according to one aspect of the present disclosure comprises a nonvolatile memory cell array unit, and a memory controller that controls a writing operation and reading operation with respect to the nonvolatile memory cell...
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WO/2023/159968A1 |
Provided in the present invention are a non-volatile memory and a programming method therefor, and a computer system. The programming method for a non-volatile memory comprises: a programming step of applying a programming pulse to a sto...
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