| Document |
Document Title |
|
WO/2015/156969A1 |
Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the pluralit...
|
|
WO/2015/149298A1 |
An Ethernet device is disclosed that may increase the speed of clock recovery operations by concurrently (1) using an adaptive loop filter to adjust a phase and frequency of an error signal to generate a filtered error signal and (2) add...
|
|
WO/2015/148003A1 |
Described is an apparatus which comprises: a comparator unit to receive at least three data signals with respective clock signals embedded in the at least three data signals, the comparator unit to provide first, second, and third clock ...
|
|
WO/2015/143980A1 |
An implementation circuit of a charge pump. The circuit comprises: a first current mirror (10), a second current mirror (11), a first switch circuit (12), a second switch circuit (13), a connecting circuit (14), a first unity gain amplif...
|
|
WO/2015/142489A1 |
Estimating a gain of a VCO in a PLL, including: means for matching to a varactor in the VCO; and means for estimating the gain of the VCO by calculating a C-V characteristic of the means for matching along with tank inductance and an out...
|
|
WO/2015/140431A1 |
The invention relates to a method for adjusting an oscillator clock frequency, comprising steps consisting in: applying a first control value (S1) to a first oscillator (OSC1); applying a second control value (S2) different from the firs...
|
|
WO/2015/136659A1 |
In a PLL circuit (1001), first of all, an output voltage (Vtune) of an LPF (50) is coupled to an ILFD (10(n)), whereby the ILFD (10(n)) becomes an oscillator. The ILFD (10(n)), a DIV (20), a PFD (30), a CP (40) and the LPF (50) form a PL...
|
|
WO/2015/137174A1 |
A surface emitting laser for emitting light with a wavelength λ includes a first reflection mirror provided on a semiconductor substrate; a resonator region including an active layer provided on the first reflection mirror; a second ref...
|
|
WO/2015/136242A1 |
A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first...
|
|
WO/2015/135490A1 |
A divisor control circuit allows a frequency divider to have a fractional divisor. The divisor control circuit includes: a multiplexer, arranged to select one of a first clock signal and a second clock signal as a multiplexed signal acco...
|
|
WO/2015/132696A1 |
A novel PLL is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits. A first terminal of each of the first and second circuits is electrically connected to an output terminal of the i-th inverte...
|
|
WO/2015/126498A2 |
A micro-electromechanical system (MEMS) frequency divider apparatus having one or more MEMS resonators on a substrate is presented. A first oscillator frequency, as an approximate multiple of the parametric oscillation frequency, is capa...
|
|
WO/2015/121780A2 |
A drive loop circuitry for a MEMS resonator. The circuitry comprises closed loop means for detecting and amplifying a signal of the MEMS resonator, means for phase shifting the detected and amplified signal, and means for feeding the det...
|
|
WO/2015/119308A1 |
The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more C...
|
|
WO/2015/120132A1 |
An apparatus and method for frequency tuning/tracking between an electrical subsystem and a mechanical transducer subsystem is presented. An electromechanical transducer generates acoustic pulses as it is driven by a transmit signal from...
|
|
WO/2015/113135A1 |
A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a s...
|
|
WO/2015/113308A1 |
Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; ...
|
|
WO/2015/116670A1 |
Tuning circuitry may include a controller that is configured to determine a phase difference for a pair of signals generated at different points in a master delay line of a master-slave delay locked loop (DLL) circuit. One of signals of ...
|
|
WO/2015/115632A1 |
An atomic oscillator includes a gas cell and a plurality of components. The plurality of components includes a temperature control device for the gas cell; an excitation light source that emits excitation light to excite atoms enclosed i...
|
|
WO/2015/112321A1 |
Certain aspects of the present disclosure provide fully differential phase detectors for use in delay-locked loops, for example. One example phase detecting circuit generally includes a first input for a reference signal; a second input ...
|
|
WO/2015/101225A1 |
An apparatus comprises a ring oscillator comprising a plurality of delay stages connected in cascade and an injection apparatus comprising a plurality of injection devices, wherein the injection devices receive a reference clock from the...
|
|
WO/2015/096368A1 |
A phase-locked loop frequency calibration circuit and a method, wherein the phase-locked loop frequency calibration circuit comprises: a timer, a counter, a control module, a frequency divider and a voltage-controlled oscillator. An outp...
|
|
WO/2015/097657A2 |
Aspects of the disclosure provide an integrated circuit (IC) (120). The IC includes a clock generation and supply voltage monitoring circuit (221) configured to monitor a supply voltage to the IC and selectively modify an operating frequ...
|
|
WO/2015/094982A1 |
A clock generation circuit is disclosed that may generate a plurality of phase-delayed signals in a manner that may be relatively immune to VCO pulling. The clock generation circuit may include a circuit to generate an oscillating signal...
|
|
WO/2015/094289A1 |
Described is an apparatus which comprises: a sampler to sample data using blind oversampling technique; an edge generator to receive sampled data and to generate quantized edge information using the sampled data; an edge filter to averag...
|
|
WO/2015/094470A1 |
Described is an apparatus which comprises: a first power supply node to provide power supply current; a ring oscillator, coupled to the first power supply node, to generate an oscillating output according to change in the power supply cu...
|
|
WO/2015/091141A1 |
An oscillator circuit (100) comprises a first, high-Q crystal oscillator (10) and a second, low-Q oscillator (20) arranged for kick-starting the crystal oscillator (10) at switch-on by coupling the second oscillator (20) to the first osc...
|
|
WO/2015/085512A1 |
A voltage-sensitive circuit, a frequency source and a voltage-controlled oscillator thereof. The voltage-controlled oscillator comprises an inductance assembly, wherein the inductance assembly comprises 2N groups of winding inductor grou...
|
|
WO/2015/085825A1 |
Disclosed are frequency calibration methods and an apparatus. One method thereof comprises: comparing a count value of a counter of a clock to be calibrated with a count value of a counter of a reference clock in real time; and when the ...
|
|
WO/2015/082009A1 |
A reference oscillator arrangement is provided for a communication apparatus capable of communicating according to a plurality of transport formats. The reference oscillator arrangement comprises a reference oscillator controller; a reso...
|
|
WO/2015/081564A1 |
A frequency synthesis method of fast locking based on phase-locked loop frequency and a circuit thereof, the method comprising the steps of: configuring data for a phase-locked loop unit when a locking timeslot starts; charging a loop fi...
|
|
WO/2015/077859A1 |
A method for correcting long-term phase drift of a crystal oscillator in a numerically- controlled oscillator is described. The method includes determining the phase error in an oscillator signal in comparison with an external time base;...
|
|
WO/2015/081241A1 |
A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and co...
|
|
WO/2015/079098A1 |
There are disclosed various methods and apparatuses for generating oscillator signals.In some embodiments the method comprises receiving a reference clock signal;obtaining a set of phase shifted reference clock signals; obtaining a phase...
|
|
WO/2015/075707A1 |
Embodiments for providing reference signal generation redundancy in distributed antenna systems (DASs) are disclosed. To avoid a single point of failure in reference signal generation that could cause components relying on the reference ...
|
|
WO/2015/074133A1 |
A digitally compensated phase locked oscillator (DCPLO) is disclosed herein. The DCPLO comprises: a DCPLO input for receiving a reference signal at a known frequency; a DCPLO output for outputting a signal at a desired frequency; a phase...
|
|
WO/2015/076789A1 |
Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a d...
|
|
WO/2015/075496A1 |
A current-to-voltage converter (101) receives a current which varies with temperature according to a selected one of two or more temperature coefficient factors and converts it to a temperature-dependent voltage which may be used as a co...
|
|
WO/2015/073659A1 |
Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback cl...
|
|
WO/2015/074067A1 |
A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the fir...
|
|
WO/2015/072679A1 |
An electronic device and a method for control of an output amplitude of a Voltage Control Oscillator (VCO) in the electronic device is provided. The electronic device includes a first circuit configured to output a frequency signal corre...
|
|
WO/2015/072649A1 |
An electronic device for compensating for process variation is provided. The electronic device includes a first circuit configured to consume a current supplied to the first circuit, and a second circuit configured to control the current...
|
|
WO/2015/069285A1 |
Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay uni...
|
|
WO/2015/062663A1 |
The invention relates to a phase lock loop (100) comprising: - a loop filter (140), - a voltage controlled oscillator (150), - a frequency divider (160), - a frequency lock detector (113), able to emit a frequency lock indication signal ...
|
|
WO/2015/061414A1 |
A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a con...
|
|
WO/2015/061622A1 |
A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based...
|
|
WO/2015/049479A1 |
This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in t...
|
|
WO/2015/045938A1 |
A biological information measurement device (1) is provided with: a phase frequency comparator (21) for outputting a deviation signal corresponding to the phase difference between a biological signal and an oscillation signal; a variable...
|
|
WO/2015/045939A1 |
The biological information measurement device (1) is provided with: a phase- and frequency-comparing part (21) for outputting a deviation signal corresponding to the phase difference between a biological signal and an oscillation signal;...
|
|
WO/2015/047280A1 |
Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupl...
|
